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Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_13openalex-snapshot
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.005openalex-snapshot
Packetization and routing analysis of on-chip multiprocessor networks
inferredcites →https://doi.org/10.1109/90.282603openalex-snapshot
On the self-similar nature of Ethernet traffic (extended version)
inferredcites →https://doi.org/10.1109/date.2004.1268972openalex-snapshot
Cost-performance trade-offs in networks on chip: a simulation-based approach
inferredcites →https://doi.org/10.1109/date.2005.22openalex-snapshot
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
inferredcites →https://doi.org/10.1109/icde.2002.994770openalex-snapshot
Data mining meets performance evaluation: fast algorithms for modeling bursty traffic
inferredcites →https://doi.org/10.1109/icvd.2001.902636openalex-snapshot
Evaluation of the traffic-performance characteristics of system-on-chip communication architectures
inferredcites →https://doi.org/10.1109/icvd.2004.1261005openalex-snapshot
The Nostrum backbone-a communication protocol stack for Networks on Chip
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/iwsoc.2004.1319892openalex-snapshot
Network on chip simulations for benchmarking
inferredcites →https://doi.org/10.1109/iwsoc.2004.49openalex-snapshot
Network on chip simulations for benchmarking
inferredcites →https://doi.org/10.1109/mc.2003.1220579openalex-snapshot
Challenges in computer architecture evaluation
inferredcites →https://doi.org/10.1109/micro.1997.645830openalex-snapshot
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
inferredcites →https://doi.org/10.1109/mm.2003.1261392openalex-snapshot
Addressing workload variability in architectural simulations
inferredcites →https://doi.org/10.1109/wwc.2001.15openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1145/288197.581193openalex-snapshot
Modelling with Generalized Stochastic Petri Nets
inferredcites →https://doi.org/10.1147/rd.272.0164openalex-snapshot
Fractal Nature of Software-Cache Interaction
inferredcites →https://doi.org/10.1201/b10980openalex-snapshot
CRC Standard Mathematical Tables and Formulae
inferredcites →https://doi.org/10.5555/968879.969127openalex-snapshot
Cost-performance trade-offs in networks on chip: a simulation-based approach
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4614-4274-5_2openalex-snapshot
NoC Modeling and Topology Exploration
inferred← citeshttps://doi.org/10.1007/978-3-540-73625-7_24openalex-snapshot
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration
inferred← citeshttps://doi.org/10.1007/s11265-008-0227-1openalex-snapshot
Evaluating SoC Network Performance in MPEG-4 Encoder
inferred← citeshttps://doi.org/10.1016/j.micpro.2008.08.010openalex-snapshot
Long-range dependence and on-chip processor traffic
inferred← citeshttps://doi.org/10.1016/j.sysarc.2007.07.004openalex-snapshot
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip
inferred← citeshttps://doi.org/10.1109/dsd.2007.4341515openalex-snapshot
On network-on-chip comparison
inferred← citeshttps://doi.org/10.1109/icecc.2011.6066624openalex-snapshot
Hybrid on-chip interconnection with coupled cores in tiles
inferred← citeshttps://doi.org/10.1109/icecs.2010.5724623openalex-snapshot
Power- and performance-aware IP mapping for NoC-based MPSoC platforms
inferred← citeshttps://doi.org/10.1109/issoc.2008.4694860openalex-snapshot
On the credibility of load-latency measurement of network-on-chips
inferred← citeshttps://doi.org/10.1109/itng.2009.186openalex-snapshot
Bus-Based and NoC Infrastructure Performance Emulation and Comparison
inferred← citeshttps://doi.org/10.1109/nocs.2010.21openalex-snapshot
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
inferred← citeshttps://doi.org/10.1109/norchp.2009.5397804openalex-snapshot
Application specific IP placement for on-chip distributed architectures
inferred← citeshttps://doi.org/10.1109/pdp.2008.52openalex-snapshot
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform
inferred← citeshttps://doi.org/10.1109/socc.2009.5335683openalex-snapshot
Parameterizing simulated annealing for distributing Kahn Process Networks on multiprocessor SoCs
inferred← citeshttps://doi.org/10.1109/tcad.2011.2149870openalex-snapshot
Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs
inferred← citeshttps://doi.org/10.11606/d.55.2008.tde-18062008-110640openalex-snapshot
Avaliação de métricas para determinar o grau de heterogeneidade de sistemas computacionais
inferred← citeshttps://doi.org/10.26053/0h-gg22-f000openalex-snapshot
Energy-efficient design of an asynchronous network-on-chip
inferred← citeshttps://doi.org/10.5120/ijca2016909552openalex-snapshot
NoCGIN: A Gamma Interconnection Network as NoC Interconnect
inferred← citeshttps://doi.org/10.6100/ir630223openalex-snapshot
Predictable mapping of streaming applications on multiprocessors
inferred← citeshttps://doi.org/10.7148/2008-0299openalex-snapshot
An Application-Oriented Synthetic Network Traffic Generator
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