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A Network Traffic Generator Model for Fast Network-on-Chip Simulation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot
QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1109/dac.2003.1218794openalex-snapshot
A timing-accurate modeling and simulation environment for networked embedded systems
inferredcites →https://doi.org/10.1109/date.2003.1253825openalex-snapshot
A practical approach for bus architecture optimization at transaction level
inferredcites →https://doi.org/10.1109/date.2004.1268966openalex-snapshot
Analyzing on-chip communication in a MPSoC environment
inferredcites →https://doi.org/10.1109/iccd.2003.1240952openalex-snapshot
Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs
inferredcites →https://doi.org/10.1145/337292.337561openalex-snapshot
Communication architecture tuners
inferredcites →https://doi.org/10.1145/378239.379045openalex-snapshot
Addressing the system-on-a-chip interconnect woes through communication-based design
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-0-387-73661-7_10openalex-snapshot
A Traffic Injection Methodology with Support for System-Level Synchronization
inferred← citeshttps://doi.org/10.1007/978-3-319-92040-5_16openalex-snapshot
Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation
inferred← citeshttps://doi.org/10.1007/978-3-540-73625-7_24openalex-snapshot
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration
inferred← citeshttps://doi.org/10.1007/978-3-642-23120-9_4openalex-snapshot
Performance and Energy Evaluation of Memory Organizations in NoC-Based MPSoCs under Latency and Task Migration
inferred← citeshttps://doi.org/10.1007/s11227-011-0678-1openalex-snapshot
An energy-aware online task mapping algorithm in NoC-based system
inferred← citeshttps://doi.org/10.1016/j.micpro.2008.03.011openalex-snapshot
Evaluating the model accuracy in automated design space exploration
inferred← citeshttps://doi.org/10.1016/j.micpro.2008.08.010openalex-snapshot
Long-range dependence and on-chip processor traffic
inferred← citeshttps://doi.org/10.1016/j.micpro.2010.01.001openalex-snapshot
A modeling tool for simulating and design of on-chip network systems
inferred← citeshttps://doi.org/10.1109/apcc.2011.6152936openalex-snapshot
Implementing and optimizing ROM table for broadcast message used in MPI unit
inferred← citeshttps://doi.org/10.1109/asap.2006.5openalex-snapshot
A Generic Multi-Phase On-Chip Traffic Generation Environment
inferred← citeshttps://doi.org/10.1109/date.2006.244109openalex-snapshot
Combining Simulation and Formal Methods for System-Level Performance Analysis
inferred← citeshttps://doi.org/10.1109/dsd.2006.52openalex-snapshot
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
inferred← citeshttps://doi.org/10.1109/dsd.2007.4341466openalex-snapshot
Evaluating the Model Accuracy in Automated Design Space Exploration
inferred← citeshttps://doi.org/10.1109/icasid.2009.5277007openalex-snapshot
Design of an on-line configurable traffic generator for NoC
inferred← citeshttps://doi.org/10.1109/iccasm.2010.5623080openalex-snapshot
A simulation environment for Network-on-Chip based on SystemC
inferred← citeshttps://doi.org/10.1109/mascot.2009.5366697openalex-snapshot
Simulation environment for design and verification of Network-on-Chip and multi-core systems
inferred← citeshttps://doi.org/10.1109/mascots.2006.9openalex-snapshot
A Statistical Traffic Model for On-Chip Interconnection Networks
inferred← citeshttps://doi.org/10.1109/norchp.2005.1596994openalex-snapshot
Requirements for network-on-chip benchmarking
inferred← citeshttps://doi.org/10.1109/tcad.2007.906990openalex-snapshot
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
inferred← citeshttps://doi.org/10.1109/tcad.2008.2010691openalex-snapshot
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
inferred← citeshttps://doi.org/10.1109/vlsid.2012.86openalex-snapshot
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip
inferred← citeshttps://doi.org/10.1109/vlsisoc.2009.6041342openalex-snapshot
Performance and energy evaluation of memory hierarchies in NoC-based MPSoCs under latency
inferred← citeshttps://doi.org/10.1145/1176254.1176277openalex-snapshot
Automatic phase detection for stochastic on-chip traffic generation
inferred← citeshttps://doi.org/10.1145/1531542.1531574openalex-snapshot
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
inferred← citeshttps://doi.org/10.1145/1878537.1878660openalex-snapshot
Comprehensive on-chip traffic generator model for SoC design and synthesis
inferred← citeshttps://doi.org/10.1145/2870633openalex-snapshot
Performance Evaluation of NoC-Based Multicore Systems
inferred← citeshttps://doi.org/10.1587/elex.6.837openalex-snapshot
Scalable distributed memory embedded system with a low-cost hardware message passing interface
inferred← citeshttps://doi.org/10.1587/transinf.e94.d.1497openalex-snapshot
A Low-Cost Standard Mode MPI Hardware Unit for Embedded MPSoC
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