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A High Level Power Model for the Nostrum NoC
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/mdt.2005.103openalex-snapshot
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1145/514049.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm
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Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays
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A Comparative Review of Adaptive Routing Approach for Network-on-Chip Router Architecture
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NoC Router Power Macro-modeling at High Level
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Cost-Based Deflection Routing for Intelligent NoC Switches
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A high level power model for Network-on-Chip (NoC) router
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Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
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A smart protocol-level task mapping for energy efficient traffic on network-on-chip
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Construction of a multidimensional plane network-on-chip architecture based on the hypercube structure
inferred← citeshttps://doi.org/10.1016/j.procs.2015.07.226openalex-snapshot
FaFNoC: A Fault-tolerant and Bufferless Network-on-chip
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.02.001openalex-snapshot
Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.05.005openalex-snapshot
Simulation environment for link energy estimation in networks-on-chip with virtual channels
inferred← citeshttps://doi.org/10.1109/conmedia.2015.7449147openalex-snapshot
UTAR NoC: Adaptive Network on Chip architecture platform
inferred← citeshttps://doi.org/10.1109/dsd.2007.4341515openalex-snapshot
On network-on-chip comparison
inferred← citeshttps://doi.org/10.1109/iccce.2008.4580777openalex-snapshot
New approach to calculate energy on NoC
inferred← citeshttps://doi.org/10.1109/isvlsi.2008.17openalex-snapshot
NoC Power Estimation at the RTL Abstraction Level
inferred← citeshttps://doi.org/10.1109/nocs.2009.5071441openalex-snapshot
Fault-tolerant architecture and deflection routing for degradable NoC switches
inferred← citeshttps://doi.org/10.1109/nocs.2016.7579325openalex-snapshot
Using benes networks at fault-tolerant and deflection routing based network-on-chips
inferred← citeshttps://doi.org/10.1109/soccon.2009.5398071openalex-snapshot
Power optimal Network-on-Chip interconnect design
inferred← citeshttps://doi.org/10.1109/tcad.2010.2048399openalex-snapshot
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
inferred← citeshttps://doi.org/10.1109/tpds.2014.2314689openalex-snapshot
On All-to-All Broadcast in Dense Gaussian Network On-Chip
inferred← citeshttps://doi.org/10.1109/tpds.2014.2346200openalex-snapshot
All-To-All Broadcast in Hexagonal Torus Networks On-Chip
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2673808openalex-snapshot
IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms
inferred← citeshttps://doi.org/10.1115/detc2011-48908openalex-snapshot
A Heterogeneous System-Level Power Macro-Modeling for Network-on-Chip Router
inferred← citeshttps://doi.org/10.1145/2228360.2228430openalex-snapshot
Explicit modeling of control and data for improved NoC router estimation
inferred← citeshttps://doi.org/10.1145/2786572.2786585openalex-snapshot
Fault-tolerant Network-on-Chip based on Fault-aware Flits and Deflection Routing
inferred← citeshttps://doi.org/10.1145/2857058.2857060openalex-snapshot
Consideration of the Flit Size for Deflection Routing based Network-on-Chips
inferred← citeshttps://doi.org/10.1145/3472754openalex-snapshot
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs
inferred← citeshttps://doi.org/10.12785/ijcds/050204openalex-snapshot
NoC Dimensioning from Mathematical Models
inferred← citeshttps://doi.org/10.26076/am8z-4b29openalex-snapshot
Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design
inferred← citeshttps://doi.org/10.3850/9783981537079_0115openalex-snapshot
PRADA: Combating Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms
inferred← citeshttps://doi.org/10.4108/icst.simutools.2014.254626openalex-snapshot
Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation
inferred← citeshttps://doi.org/10.48550/arxiv.1912.05670openalex-snapshot
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs
inferred← citeshttps://doi.org/10.5121/csit.2014.41000openalex-snapshot
Computer Science & Information Technology ( CS & IT )
inferred← citeshttps://doi.org/10.5121/csit.2014.41003openalex-snapshot
Tribasim : A Novel Network on Chip Simulator Based on System C
inferred← citeshttps://doi.org/10.70675/4cc52fddze3c6z4a94zb61dz91b90592db88openalex-snapshot
Worst-case delay analysis of core-to-IO flows over many-cores architectures
inferred← citeshttps://doi.org/10.70675/e0befbefz4007z4f07z932bz6e6f573f0703openalex-snapshot
Vers le support des systèmes à criticité mixte sur des architectures NoC
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