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Networks on Chip

https://doi.org/10.1007/b105353
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A Reconfigurable On‐Chip Interconnection Network for Large Multicore Systems
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PDNOC: Partially diagonal network‐on‐chip for high efficiency multicore systems
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A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC
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Improving Networks‐on‐Chip performability: A topology‐based approach
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Heterogeneous System-Level Specification in Systemc
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Socket-Based Design Using Decoupled Interconnects
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Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
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Evolutionary Design of Group Communication Schedules for Interconnection Networks
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Evolutionary Design of OAB and AAB Communication Schedules for Interconnection Networks
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A New System C-Based Foundation for the CE Curriculum
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xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
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Timed Asynchronous Circuits Modeling and Validation Using SystemC
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Three-Dimensional Network-on-Chip Architecture
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A Protocol Stack Architecture for Optical Network-on-Chip
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Physical Analysis of NoC Topologies for 3-D Integrated Systems
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Asynchronous 3D-NoCs Making Use of Serialized Vertical Links
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Performance-Energy Tradeoffs for Noc Reliability
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Introduction
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Network-on-Chip Technology: A Paradigm Shift
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Communication Architecture
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NoC Verification and Testing
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Learning-Based Routing Algorithms for On-Chip Networks
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Energy-Efficient Networks-on-Chip Architectures: Design and Run-Time Optimization
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Introduction
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Introduction
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An Asynchronous 2D-Torus Network-on-Chip Using Adaptive Routing Algorithm
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HIBI v.2 Communication Network for System-on-Chip
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Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation
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A Link-Load Balanced Low Energy Mapping and Routing for NoC
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Power Consumption and Performance Analysis of 3D NoCs
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SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs
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Physical Design Issues in 3-D Integrated Technologies
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A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoC
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FIFO Optimization for Energy-Performance Trade-off in Mesh-of-Tree Based Network-on-Chip
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Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths
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Multicast Algorithm for 2D de Bruijn NoCs
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Methods for the Design and Development
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PDNOC: An Efficient Partially Diagonal Network-on-Chip Design
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Hierarchical Agents Based Fault-Tolerant and Congestion-Aware Routing for NoC
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A Low-Latency Virtual-Channel Router with Optimized Pipeline Stages for On-Chip Network
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Fault-Tolerant Optimization for Application-Specific Network-on-Chip Architecture
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3D Bidirectional-Channel Routing Algorithm for Network-Based Many-Core Embedded Systems
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An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks
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Network adapter architectures in network on chip: comprehensive literature review
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QoS-supported On-chip Communication for Multi-processors
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Link Testing: a Survey of Current Trends in Network on Chip
inferred← citeshttps://doi.org/10.1007/s11227-015-1617-3openalex-snapshot
HHS: an efficient network topology for large-scale data centers
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A flexible and high-performance data center network topology
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Reliable congestion-aware path prediction mechanism in 2D NoCs based on EFuNN
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Machine learning-driven performance assessment of network-on-chip architectures
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Constructive heuristic-based router placement in thermal- and performance-aware area-constrained planar Application-Specific NoC design (TPAP-ASNoC)
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HIBI Communication Network for System-on-Chip
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Adaptive real-time image processing exploiting two dimensional reconfigurable architecture
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Performance comparison of some shared memory organizations for 2D mesh-like NOCs
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SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems
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A high performance reliable NoC router
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System-on-package: a broad perspective from system design to technology development
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Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip
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Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems
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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application
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Fully adaptive routing algorithms and region‐based approaches for two‐dimensional and three‐dimensional networks‐on‐chip
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Performance/energy aware task migration algorithm for many‐core chips
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Comparative analysis of network‐on‐chip simulation tools
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DICA: destination intensity and congestion‐aware output selection strategy for network‐on‐chip systems
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Low-power and error protection coding for network-on-chip traffic
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Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism[Note 1]
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Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols
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Implementation of guaranteed services in the MANGO clockless network-on-chip
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Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification
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Concurrency Model for Network-On-Chip Design Architecture
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A MULTI-PATH ROUTING SCHEME FOR TORUS-BASED NOCs1
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On a Web-Graph-Based Micronetwork Architecture for SoCs
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Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures
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A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack
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HIBS — Novel inter-layer bus structure for stacked architectures
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A Novel Architecture with Low Laser Power Based on Optical Networks-on-Chip
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Exploring and optimizing crosstalk effect in VCmesh-based optical networks-on-chip
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An Efficient Algorithm for Mapping Real Time Embedded Applications on NoC Architecture
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Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router
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Asynchronous Packet-Switching for Networks-on-Chip
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Models of Computation for Networks on Chip
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SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications
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Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance
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An adaptive fuzzy logic-based routing algorithm for networks-on-chip
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Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay
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A scalable distributed memory architecture for Network on Chip
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Communication-Centric SoC Design for Nanoscale Domain
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Using TLM for Exploring Bus-based SoC Communication Architectures
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A test method for delay faults in NoC interconnects
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Speedup analysis of data-parallel applications on Multi-core NoCs
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Trends of terascale computing Chips in the next ten years
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Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
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Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
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Frequent value compression in packet-based NoC architectures
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Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems
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Network-on-Chip router design with Buffer-Stealing
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ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures
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A High Performance Reliable NoC Router
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An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
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A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
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Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
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Design and Implementation of a GALS Adapter for ANoC Based Architectures
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A novel fuzzy logic based bufferless routing algorithm for low-power NoCs
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Diagnostic modeling of microprocessors with high-level decision diagrams
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Bio-inspired thermal management techniques for three dimensional heterogeneous stacked network-on-chip systems
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Pipeline-based interlayer bus structure for 3D networks-on-chip
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Exploring a low-cost inter-layer communication scheme for 3D networks-on-chip
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A scheduling approach for packet-switched on-chip networks
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ftNoC: A New Architecture of Network on Chip with Fault-Tolerance
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QOS Driven Network-on-Chip Design for Real Time Systems
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Flexible simulation and modeling for 2D topology NoC system design
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A case study of the Odd-Even turn model
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NoC architecture with local bus design for network coding
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MSNS: A Top-Down MPI-Style Hierarchical Simulation Framework for Network-on-Chip
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Design of a low latency network interface using dual buffer for network on chip
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UTAR NoC: Adaptive Network on Chip architecture platform
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A scalable and reconfigurable verification and benchmark environment for Network on Chip architecture
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A NoC Simulation and Verification Platform Based on SystemC
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System-on-chip beyond the nanometer wall
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Design space exploration and prototyping for on-chip multimedia applications
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Prediction-based flow control for network-on-chip traffic
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×pipesCompiler: a tool for instantiating application specific networks on chip
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Distributed multimedia system design: a holistic perspective
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Application of a multi-processor SoC platform to high-speed packet forwarding
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OCCN: a network-on-chip modeling and simulation framework
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A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip
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An Application-Specific Design Methodology for STbus Crossbar Generation
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Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
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A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
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A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method
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Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
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Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor
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Multicast Parallel Pipeline Router Architecture for Network-on-Chip
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Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
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Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller
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Design-for-Test of Asynchronous Networks-on-Chip
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Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip
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Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents
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A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip
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A Load-Balanced Routing Scheme for NoC-Based Systems-on-Chip
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NoCs: a new contract between hardware and software
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A two-step genetic algorithm for mapping task graphs to a network on chip architecture
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Automatic mapping of parallel applications onto multi-processor platforms: a multimedia application
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Reliability and power management of integrated systems
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Workload simulation method for evaluation of application feasibility in a mobile multiprocessor platform
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Packetizing OCP Transactions in the MANGO Network-on-Chip
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A High Level Power Model for the Nostrum NoC
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GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors
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On network-on-chip comparison
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NoC Topologies Exploration based on Mapping and Simulation Models
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Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip
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Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources
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Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms
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Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems
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LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture
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Cost of Sparse Mesh Layouts Supporting Throughput Computing
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Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures
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Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm
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Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy
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Adaptive Networks-on-Chip Routing with Fuzzy Logic Control
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Transaction level modeling of an OSI-like layered NoC
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A reliability-aware design methodology for Networks-on-Chip applications
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Towards hierarchical cluster based cache coherence for large-scale network-on-chip
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Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers
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An Emulation Solution for the SegBus Platform
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Networks on Chips: Scalable interconnects for future systems on chips
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Design of Distributed Storage Multi-core System Based on NoC Architecture
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Simulation and synthesis of networks-on-chip by using NoCSimp HDL library
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Power-Aware Mapping for Network-on-Chip Architectures under Bandwidth and Latency Constraints
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A Numerical Solution for Throughput Improvement of On-chip Irregular Mesh Interconnection Network
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A DFT Architecture for Asynchronous Networks-on-Chip
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Addressing transient routing errors in fault-tolerant Networks-on-Chips
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An automated technique for design of custom Network-on-Chip topologies
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Incorporating MPLS for Better SoC Utilization and Traffic Engineering
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Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications
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Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol
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Modeling of Data Delivery Modes of Next Generation SOC-NOC Router
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Switch Design and Implementation for Network-on-Chip
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Switch Design and Implementation for Network-on-Chip
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Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method
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SupermarQ: A Scalable Quantum Benchmark Suite
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Low power heterogeneous 3D Networks-on-Chip architectures
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Towards balanced traffic distribution in NoCs using a highly adaptive path-based routing algorithm
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The Shuffle-Exchange Mesh Topology for 3D NoCs
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Using an MDE Approach for Modeling of Interconnection Networks
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An MPLS-based fat tree Network-on-Chip systems
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Adaptive routing scheme for NoC communication architecture
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Analysis of Network on Chip Topologies
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A systemC-based NoC simulation framework supporting heterogeneous communicators
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A network-on-Chip system-level simulation environment supporting asynchronous router
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Communication-aware task scheduling and voltage selection for total systems energy minimization
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Transaction level modeling in practice: Motivation and introduction
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A novel hardware method to implement a routing algorithm onto Network on Chip
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Efficient run-time task allocation in reconfigurable multiprocessor System-on-Chip with Network-on-Chip
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Phoenix NoC: A distributed fault tolerant architecture
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MP-DPI: A network processing platform based on the many-core processor
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A hybird hierarchical architecture for 3D multi-cluster NoC
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A Dynamic Fuzzy Logic Based Routing Scheme for Bufferless NoCs
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Fault-Tolerance Ring Network on Chip without Buffer
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A low cost serious failure tolerance solution in unreliable NoCs
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