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Coverage-Driven Stimuli Generation

https://doi.org/10.1109/dsd.2012.37
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/0-387-30784-2openalex-snapshot
Constraint-Based Verification
inferredcites →https://doi.org/10.1007/0-387-31275-7openalex-snapshot
Writing Testbenches using System Verilog
inferredcites →https://doi.org/10.1007/3-540-49059-0_14openalex-snapshot
Symbolic Model Checking without BDDs
inferredcites →https://doi.org/10.1007/978-90-481-9304-2_14openalex-snapshot
SMT-based Stimuli Generation in the SystemC Verification Library
inferredcites →https://doi.org/10.1109/54.936247openalex-snapshot
Coverage metrics for functional validation of hardware designs
inferredcites →https://doi.org/10.1109/aspdac.2007.358110openalex-snapshot
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
inferredcites →https://doi.org/10.1109/date.2005.162openalex-snapshot
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
inferredcites →https://doi.org/10.1109/iccad.1993.580110openalex-snapshot
Verification of large synthesized designs
inferredcites →https://doi.org/10.1109/iccad.2007.4397275openalex-snapshot
Stimulus generation for constrained random simulation
inferredcites →https://doi.org/10.1109/isvlsi.2007.33openalex-snapshot
Coverage Driven Verification applied to Embedded Software
inferredcites →https://doi.org/10.1145/1127908.1127920openalex-snapshot
HW/SW co-verification of embedded systems using bounded model checking
inferredcites →https://doi.org/10.21236/ada360973openalex-snapshot
Symbolic Model Checking without BDDs
inferredcites →https://doi.org/10.5555/259794.259883openalex-snapshot
Verification of large synthesized designs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/dsd.2013.55openalex-snapshot
Minimal Stimuli Generation in Simulation-Based Verification
inferred← citeshttps://doi.org/10.1109/eamta.2014.6906084openalex-snapshot
Coverage modeling for verification of floating point arithmetic units
inferred← citeshttps://doi.org/10.1109/eurosp68448.2026.00078openalex-snapshot
High Impedance: Analysis of Publicly Disclosed Vulnerabilities in FPGA IP Cores
inferred← citeshttps://doi.org/10.1109/iscas.2019.8702140openalex-snapshot
Exact Stimuli Minimization for Simulation-Based Verification
inferred← citeshttps://doi.org/10.1109/isocc.2013.6864032openalex-snapshot
Coverage-directed stimulus generation using a genetic algorithm
inferred← citeshttps://doi.org/10.1109/latw.2014.6841904openalex-snapshot
Simplified stimuli generation for scenario and assertion based verification
inferred← citeshttps://doi.org/10.1109/mwscas47672.2021.9531876openalex-snapshot
Enhancing Testbench Quality via Genetic Algorithm
inferred← citeshttps://doi.org/10.1109/tcad.2016.2611494openalex-snapshot
Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification
inferred← citeshttps://doi.org/10.1145/2651400openalex-snapshot
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
inferred← citeshttps://doi.org/10.1145/2660540.2660979openalex-snapshot
Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification
inferred← citeshttps://doi.org/10.1145/3241403.3241432openalex-snapshot
Model-based engineering & simulation of software-intensive systems-of-systems
inferred← citeshttps://doi.org/10.11606/t.55.2018.tde-06072018-110150openalex-snapshot
A simulation-driven model-based approach for designing software-intensive systems-of-systems architectures
inferred← citeshttps://doi.org/10.1186/s13173-017-0062-yopenalex-snapshot
Stimuli-SoS: a model-based approach to derive stimuli generators for simulations of systems-of-systems software architectures
inferred← citeshttps://doi.org/10.1587/transfun.e100.a.1481openalex-snapshot
Coverage-Driven Design Verification Using a Diverse SAT Solver
inferred← citeshttps://doi.org/10.1587/transfun.e101.a.1053openalex-snapshot
Applying an SMT Solver to Coverage-Driven Design Verification
inferred← citeshttps://doi.org/10.2197/ipsjtsldm.16.45openalex-snapshot
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage
inferred← citeshttps://doi.org/10.22360/springsim.2019.tms.005openalex-snapshot
Modeling & Simulation of Software Architectures of Systems-of-Systems : An Industrial Report on the Brazilian Space System
inferred← citeshttps://doi.org/10.23919/date.2017.7927021openalex-snapshot
MINIME-validator: Validating hardware with synthetic parallel testcases
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474160openalex-snapshot
Automatic Scalable System for the Coverage-Directed Generation (CDG) Problem
inferred← citeshttps://doi.org/10.23919/springsim.2019.8732870openalex-snapshot
Modeling & Simulation Of Software Architectures Of Systems-Of-Systems: An Industrial Report On The Brazilian Space System
inferred← citeshttps://doi.org/10.70675/05002429za36bz4ebazbb6cz7f570ad34ddfopenalex-snapshot
A simulation-driven model-based approach for designing softwareintensive systems-of-systems architectures
inferred← citeshttps://doi.org/10.7567/jjap.56.04cf15openalex-snapshot
Property-driven functional verification technique for high-speed vision system-on-chip processor
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