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A DFT Architecture for Asynchronous Networks-on-Chip

https://doi.org/10.1109/ets.2006.3

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_8openalex-snapshot

Networks on Chips

inferredcites →https://doi.org/10.1007/b105353openalex-snapshot

Networks on Chip

inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot

QNoC: QoS architecture and design process for network on chip

inferredcites →https://doi.org/10.1016/j.vlsi.2004.03.003openalex-snapshot

HERMES: an infrastructure for low area overhead packet-switching networks on chip

inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot

Networks on chips: a new SoC paradigm

inferredcites →https://doi.org/10.1109/async.1998.666491openalex-snapshot

ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor

inferredcites →https://doi.org/10.1109/async.2003.1199173openalex-snapshot

Delay-insensitive, point-to-point interconnect using m-of-n codes

inferredcites →https://doi.org/10.1109/async.2005.10openalex-snapshot

An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework

inferredcites →https://doi.org/10.1109/date.2000.840047openalex-snapshot

A generic architecture for on-chip packet-switched interconnections

inferredcites →https://doi.org/10.1109/date.2003.1253633openalex-snapshot

Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip

inferredcites →https://doi.org/10.1109/delta.2002.994599openalex-snapshot

Interconnect IP node for future system-on-chip designs

inferredcites →https://doi.org/10.1109/iccd.2003.1240952openalex-snapshot

Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

inferredcites →https://doi.org/10.1109/iccd.2012.6378615openalex-snapshot

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs

inferredcites →https://doi.org/10.1109/ipdps.2003.1213180openalex-snapshot

SoCBUS: switched network on chip for hard real time embedded systems

inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot

A network on chip architecture and design methodology

inferredcites →https://doi.org/10.1109/mcom.2003.1232240openalex-snapshot

Bringing communication networks on a chip: test and verification implications

inferredcites →https://doi.org/10.1109/mm.2002.1044296openalex-snapshot

Chain: a delay-insensitive chip area interconnect

inferredcites →https://doi.org/10.1109/mm.2004.1268991openalex-snapshot

Asynchronous interconnect for synchronous soc design

inferredcites →https://doi.org/10.1109/tcad.2004.829796openalex-snapshot

Indirect Test Architecture for SoC Testing

inferredcites →https://doi.org/10.1109/test.1998.743146openalex-snapshot

Testing embedded-core based system chips

inferredcites →https://doi.org/10.1109/test.2005.1584020openalex-snapshot

A scalable test strategy for network-on-chip routers

inferredcites →https://doi.org/10.1145/1027084.1027088openalex-snapshot

Reusing an on-chip network for the test of core-based systems

inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot

A generic architecture for on-chip packet-switched interconnections

inferredcites →https://doi.org/10.1145/378239.379047openalex-snapshot

On-chip communication architecture for OC-768 network processors

inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot

Route packets, net wires

inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s10836-024-06104-yopenalex-snapshot

Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems

inferred← citeshttps://doi.org/10.1049/iet-cdt.2008.0072openalex-snapshot

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

inferred← citeshttps://doi.org/10.1109/ats.2007.97openalex-snapshot

An HDL-Based Platform for High Level NoC Switch Testing

inferred← citeshttps://doi.org/10.1109/commantel.2013.6482432openalex-snapshot

Asynchronous circuit verification: From specification to circuit

inferred← citeshttps://doi.org/10.1109/date.2007.364618openalex-snapshot

Using the Inter- and Intra-Switch Regularity in NoC Switch Testing

inferred← citeshttps://doi.org/10.1109/ddecs.2006.1649605openalex-snapshot

Design-for-Test of Asynchronous Networks-on-Chip

inferred← citeshttps://doi.org/10.1109/dft.2007.55openalex-snapshot

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model

inferred← citeshttps://doi.org/10.1109/ets.2007.30openalex-snapshot

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints

inferred← citeshttps://doi.org/10.1109/issoc.2011.6089219openalex-snapshot

Impact of proactive temperature management on performance of Networks-on-Chip

inferred← citeshttps://doi.org/10.1109/mcsoc.2012.13openalex-snapshot

Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels

inferred← citeshttps://doi.org/10.1109/nocs.2008.4492734openalex-snapshot

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application

inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2271697openalex-snapshot

On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures

inferred← citeshttps://doi.org/10.18419/opus-3585openalex-snapshot

Self-diagnosis in Network-on-Chips

inferred← citeshttps://doi.org/10.4018/978-1-4666-6034-2.ch015openalex-snapshot

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

inferred← citeshttps://doi.org/10.4018/jertcs.2012100102openalex-snapshot

Performance Analysis of Temperature Management Approaches in Networks-on-Chip

inferred← citeshttps://doi.org/10.4218/etrij.08.0107.0090openalex-snapshot

NoC-Based SoC Test Scheduling Using Ant Colony Optimization

inferred← citeshttps://doi.org/10.5555/1266366.1266443openalex-snapshot

Using the inter- and intra-switch regularity in NoC switch testing

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