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Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism

https://doi.org/10.1109/ets.2006.48

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/b978-0-12-370480-1.x5000-2openalex-snapshot

Network Analysis, Architecture, and Design

inferredcites →https://doi.org/10.1049/pbte077e_ch4openalex-snapshot

Network analysis, architecture, and design

inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot

Networks on chips: a new SoC paradigm

inferredcites →https://doi.org/10.1109/async.2005.7openalex-snapshot

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

inferredcites →https://doi.org/10.1109/test.1998.743146openalex-snapshot

Testing embedded-core based system chips

inferredcites →https://doi.org/10.1109/test.2000.894302openalex-snapshot

Wrapper design for embedded core test

inferredcites →https://doi.org/10.1109/vts.2005.66openalex-snapshot

Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking

inferredcites →https://doi.org/10.1145/1027084.1027088openalex-snapshot

Reusing an on-chip network for the test of core-based systems

inferredcites →https://doi.org/10.1145/944027.944029openalex-snapshot

SOC test architecture design for efficient utilization of test bandwidth

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4614-0791-1_5openalex-snapshot

Advanced Approaches for NoC Reuse

inferred← citeshttps://doi.org/10.1007/s10617-011-9074-6openalex-snapshot

A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks

inferred← citeshttps://doi.org/10.1016/b978-012373973-5.50009-7openalex-snapshot

System/Network-On-Chip Test Architectures

inferred← citeshttps://doi.org/10.1016/j.mejo.2010.04.014openalex-snapshot

An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip

inferred← citeshttps://doi.org/10.1016/j.mejo.2011.03.002openalex-snapshot

BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards

inferred← citeshttps://doi.org/10.1016/j.mejo.2012.12.003openalex-snapshot

A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC

inferred← citeshttps://doi.org/10.1049/iet-cdt.2008.0072openalex-snapshot

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

inferred← citeshttps://doi.org/10.1093/ietisy/e91-d.7.1999openalex-snapshot

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time

inferred← citeshttps://doi.org/10.1093/ietisy/e91-d.7.2008openalex-snapshot

NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints

inferred← citeshttps://doi.org/10.1109/atc.2009.5349340openalex-snapshot

An asynchronous low-power innovative network-On-chip including design-for-test capabilities

inferred← citeshttps://doi.org/10.1109/ats.2007.22openalex-snapshot

Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing

inferred← citeshttps://doi.org/10.1109/date.2007.364618openalex-snapshot

Using the Inter- and Intra-Switch Regularity in NoC Switch Testing

inferred← citeshttps://doi.org/10.1109/date.2008.4484917openalex-snapshot

Re-Examining the Use of Network-on-Chip as Test Access Mechanism

inferred← citeshttps://doi.org/10.1109/date.2010.5457239openalex-snapshot

A fully-asynchronous low-power framework for GALS NoC integration

inferred← citeshttps://doi.org/10.1109/date.2012.6176601openalex-snapshot

Test pin count reduction for NoC-based Test delivery in multicore SOCs

inferred← citeshttps://doi.org/10.1109/delta.2008.29openalex-snapshot

Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction

inferred← citeshttps://doi.org/10.1109/ets.2007.30openalex-snapshot

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints

inferred← citeshttps://doi.org/10.1109/icasid.2010.5551837openalex-snapshot

Design and implemetion of DDR2 wrapper for cluster based MPSoC

inferred← citeshttps://doi.org/10.1109/iscas.2009.5118263openalex-snapshot

A Scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems

inferred← citeshttps://doi.org/10.1109/isvlsi.2008.86openalex-snapshot

Improving the Test of NoC-Based SoCs with Help of Compression Schemes

inferred← citeshttps://doi.org/10.1109/itc50671.2022.00030openalex-snapshot

Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus

inferred← citeshttps://doi.org/10.1109/itcs.2010.5581281openalex-snapshot

A Fast Test Architecture for Asynchronous Network-on-Chip Routing Networks

inferred← citeshttps://doi.org/10.1109/nocs.2008.4492734openalex-snapshot

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application

inferred← citeshttps://doi.org/10.1109/peits.2009.5406770openalex-snapshot

The new test wrapper design for core testing in packet-switched micro-network on chip

inferred← citeshttps://doi.org/10.1109/tc.2013.82openalex-snapshot

Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs

inferred← citeshttps://doi.org/10.1109/tcad.2012.2205385openalex-snapshot

EDT Bandwidth Management in SoC Designs

inferred← citeshttps://doi.org/10.1109/tcad.2014.2311394openalex-snapshot

Test-Delivery Optimization in Manycore SOCs

inferred← citeshttps://doi.org/10.1109/tdsc.2009.53openalex-snapshot

Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays

inferred← citeshttps://doi.org/10.1109/test.2010.5699227openalex-snapshot

Dynamic channel allocation for higher EDT compression in SoC designs

inferred← citeshttps://doi.org/10.1109/test.2011.6139170openalex-snapshot

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

inferred← citeshttps://doi.org/10.1109/test.2012.6401535openalex-snapshot

A dynamic programming solution for optimizing test delivery in multicore SOCs

inferred← citeshttps://doi.org/10.1109/vdat.2009.5158098openalex-snapshot

Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems

inferred← citeshttps://doi.org/10.1109/vts.2007.26openalex-snapshot

DfT for the Reuse of Networks-on-Chip as Test Access Mechanism

inferred← citeshttps://doi.org/10.1109/vts.2010.5469570openalex-snapshot

Reusing NoC-infrastructure for test data compression

inferred← citeshttps://doi.org/10.1109/vts.2014.6818797openalex-snapshot

Test-time optimization in NOC-based manycore SOCs using multicast routing

inferred← citeshttps://doi.org/10.1145/1403375.1403571openalex-snapshot

Re-examining the use of network-on-chip as test access mechanism

inferred← citeshttps://doi.org/10.12681/eadd/17988openalex-snapshot

Μεθοδολογίες δοκιμής για πολυεπεξεργαστές και πολυπύρηνα ολοκληρωμένα κυκλώματα

inferred← citeshttps://doi.org/10.14257/ijca.2013.6.5.23openalex-snapshot

Novel Core Test Wrapper Design Supporting Multi-mode Testing of NoC-based SoC

inferred← citeshttps://doi.org/10.4218/etrij.08.0107.0090openalex-snapshot

NoC-Based SoC Test Scheduling Using Ant Colony Optimization

inferred← citeshttps://doi.org/10.5555/1266366.1266443openalex-snapshot

Using the inter- and intra-switch regularity in NoC switch testing

inferred← citeshttps://doi.org/10.5555/1870926.1870938openalex-snapshot

A fully-asynchronous low-power framework for GALS NoC integration

inferred← citeshttps://doi.org/10.5555/2492708.2492904openalex-snapshot

Test pin count reduction for NoC-based test delivery in multicore SOCs

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