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Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms

https://doi.org/10.1109/fpl.2011.20
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-45787-9_68openalex-snapshot
A Viscous Fluid Model for Multimodal Non-rigid Image Registration Using Mutual Information
inferredcites →https://doi.org/10.1007/bfb0046964openalex-snapshot
Fast Fluid Registration of medical images
inferredcites →https://doi.org/10.1007/s11554-007-0028-yopenalex-snapshot
FPGA-based real-time 3D image preprocessing for image-guided medical interventions
inferredcites →https://doi.org/10.1016/0165-1684(95)00020-eopenalex-snapshot
Recursive implementation of the Gaussian filter
inferredcites →https://doi.org/10.1016/j.media.2009.06.002openalex-snapshot
Comparing registration methods for mapping brain change using tensor-based morphometry
inferredcites →https://doi.org/10.1016/s1361-8415(03)00039-2openalex-snapshot
A viscous fluid model for multimodal non-rigid image registration using mutual information
inferredcites →https://doi.org/10.1093/acprof:oso/9780198528418.001.0001openalex-snapshot
Numerical Methods for Image Registration
inferredcites →https://doi.org/10.1109/83.536892openalex-snapshot
Deformable templates using large deformation kinematics
inferredcites →https://doi.org/10.1109/cvpr.1996.517081openalex-snapshot
Non-rigid matching using demons
inferredcites →https://doi.org/10.1109/date.2009.5090789openalex-snapshot
Automated synthesis of streaming C applications to process networks in hardware
inferredcites →https://doi.org/10.1109/fccm.2009.19openalex-snapshot
More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control
inferredcites →https://doi.org/10.1109/sasp.2011.5941081openalex-snapshot
3D recursive Gaussian IIR on GPU and FPGAs — A case for accelerating bandwidth-bounded applications
inferredcites →https://doi.org/10.1109/tbcas.2007.909023openalex-snapshot
FPGA-Accelerated Deformable Image Registration for Improved Target-Delineation During CT-Guided Interventions
inferredcites →https://doi.org/10.1109/tcad.2009.2013541openalex-snapshot
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/titb.2003.821370openalex-snapshot
FAIR: a hardware architecture for real-time 3-D image registration
inferredcites →https://doi.org/10.1137/0731032openalex-snapshot
Signal and Image Restoration Using Shock Filters and Anisotropic Diffusion
inferredcites →https://doi.org/10.1145/1542275.1542313openalex-snapshot
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
inferredcites →https://doi.org/10.1145/2024724.2024937openalex-snapshot
A reuse-aware prefetching scheme for scratchpad memory
inferredcites →https://doi.org/10.2352/j.imagingsci.technol.2005.49.2.art00002openalex-snapshot
Hardware Acceleration of Mutual Information-Based 3D Image Registration
inferredcites →https://doi.org/10.5555/1874620.1874837openalex-snapshot
Automated synthesis of streaming C applications to process networks in hardware

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s00607-014-0434-5openalex-snapshot
A new memory mapping mechanism for GPGPUs’ stencil computation
inferred← citeshttps://doi.org/10.1007/s11227-018-2443-1openalex-snapshot
Optimizing inter-nest data locality in imperfect stencils based on loop blocking
inferred← citeshttps://doi.org/10.1007/s11554-017-0722-3openalex-snapshot
High-level synthesis for FPGAs: code optimization strategies for real-time image processing
inferred← citeshttps://doi.org/10.1109/asap.2011.6043279openalex-snapshot
Domain-specific processor with 3D integration for medical image processing
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6165071openalex-snapshot
Platform characterization for Domain-Specific Computing
inferred← citeshttps://doi.org/10.1109/codes-isss.2013.6659002openalex-snapshot
Improving polyhedral code generation for high-level synthesis
inferred← citeshttps://doi.org/10.1109/hipc.2016.040openalex-snapshot
Automatic Code Generation for Iterative Multi-dimensional Stencil Computations
inferred← citeshttps://doi.org/10.1145/2304576.2304619openalex-snapshot
High-performance code generation for stencil computations on GPU architectures
inferred← citeshttps://doi.org/10.1145/2435264.2435271openalex-snapshot
Improving high level synthesis optimization opportunity through polyhedral transformations
inferred← citeshttps://doi.org/10.1145/2435264.2435273openalex-snapshot
Polyhedral-based data reuse optimization for configurable computing
inferred← citeshttps://doi.org/10.1145/2830018.2830025openalex-snapshot
SDSLc
inferred← citeshttps://doi.org/10.1587/transinf.e97.d.1225openalex-snapshot
Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh
inferred← citeshttps://doi.org/10.23919/fpl.2017.8056781openalex-snapshot
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs
inferred← citeshttps://doi.org/10.32657/10356/61735openalex-snapshot
Architectural and algorithmic design for embedded medical imaging
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