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A reuse-aware prefetching scheme for scratchpad memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/tc.2009.188openalex-snapshot
Scratchpad Memory Management Techniques for Code in Embedded Systems without an MMU
inferredcites →https://doi.org/10.1145/1024393.1024416openalex-snapshot
Compiler orchestrated prefetching via speculation and predication
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1119772.1119788openalex-snapshot
Data partitioning for maximal scratchpad usage
inferredcites →https://doi.org/10.1145/1345206.1345210openalex-snapshot
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories
inferredcites →https://doi.org/10.1145/1356058.1356079openalex-snapshot
Prefetching irregular references for software cache on cell
inferredcites →https://doi.org/10.1145/143365.143488openalex-snapshot
Design and evaluation of a compiler algorithm for prefetching
inferredcites →https://doi.org/10.1145/1582710.1582711openalex-snapshot
Compiler-directed scratchpad memory management via graph coloring
inferredcites →https://doi.org/10.1145/378239.379049openalex-snapshot
Dynamic management of scratch-pad memory space
inferredcites →https://doi.org/10.1145/502217.502221openalex-snapshot
Storage allocation for embedded processors
inferredcites →https://doi.org/10.1145/513918.514077openalex-snapshot
Compiler-directed scratch pad memory hierarchy design and management
inferredcites →https://doi.org/10.1145/581888.581891openalex-snapshot
An optimal memory allocation scheme for scratch-pad-based embedded systems
inferredcites →https://doi.org/10.1145/951710.951747openalex-snapshot
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
inferredcites →https://doi.org/10.5555/1509456.1509582openalex-snapshot
SPM management using Markov chain based data access prediction
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.5512openalex-snapshot
Static code transformations for thread‐dense memory accesses in GPU computing
inferred← citeshttps://doi.org/10.1007/s11042-015-2721-3openalex-snapshot
An efficient Markov chain-based data prefetching for motion estimation of HEVC on multi-core DSPs
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.05.001openalex-snapshot
A predictable hardware to exploit temporal reuse in real-time and embedded systems
inferred← citeshttps://doi.org/10.1109/access.2016.2635378openalex-snapshot
High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?
inferred← citeshttps://doi.org/10.1109/asap.2011.6043279openalex-snapshot
Domain-specific processor with 3D integration for medical image processing
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6164955openalex-snapshot
An integrated and automated memory optimization flow for FPGA behavioral synthesis
inferred← citeshttps://doi.org/10.1109/clei.2015.7359462openalex-snapshot
Scratchpad memory management using data-prefetching
inferred← citeshttps://doi.org/10.1109/dasip.2016.7853816openalex-snapshot
FPGA memory optimization for real-time imaging
inferred← citeshttps://doi.org/10.1109/fccm.2014.12openalex-snapshot
A Fully Pipelined and Dynamically Composable Architecture of CGRA
inferred← citeshttps://doi.org/10.1109/fpl.2011.20openalex-snapshot
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms
inferred← citeshttps://doi.org/10.1109/fpl.2015.7293983openalex-snapshot
OpenCL computing on FPGA using multiported
inferred← citeshttps://doi.org/10.1109/icsai.2012.6223148openalex-snapshot
HVSM: An approach to exploiting the locality of the multi-node heterogeneous multicore system
inferred← citeshttps://doi.org/10.1109/iscas.2013.6572078openalex-snapshot
Designing scratchpad memory architecture with emerging STT-RAM memory technologies
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00018openalex-snapshot
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
inferred← citeshttps://doi.org/10.1109/tcad.2017.2648838openalex-snapshot
Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse
inferred← citeshttps://doi.org/10.1142/9781783266975_0001openalex-snapshot
Accelerator-Rich Architectures — Computing Beyond Processors
inferred← citeshttps://doi.org/10.1145/2145816.2145856openalex-snapshot
Optimizing remote accesses for offloaded kernels
inferred← citeshttps://doi.org/10.1145/2228360.2228586openalex-snapshot
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis
inferred← citeshttps://doi.org/10.1145/2333660.2333717openalex-snapshot
Static and dynamic co-optimizations for blocks mapping in hybrid caches
inferred← citeshttps://doi.org/10.1145/2370036.2145856openalex-snapshot
Optimizing remote accesses for offloaded kernels
inferred← citeshttps://doi.org/10.1145/2380403.2380440openalex-snapshot
Integrating software caches with scratch pad memory
inferred← citeshttps://doi.org/10.1145/2800788openalex-snapshot
Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System
inferred← citeshttps://doi.org/10.1145/2847263.2847264openalex-snapshot
Efficient Memory Partitioning for Parallel Data Access via Data Reuse
inferred← citeshttps://doi.org/10.1145/2926697.2926702openalex-snapshot
Characterizing emerging heterogeneous memory
inferred← citeshttps://doi.org/10.1145/2934680openalex-snapshot
Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory--Based Architectures
inferred← citeshttps://doi.org/10.1145/3241624.2926702openalex-snapshot
Characterizing emerging heterogeneous memory
inferred← citeshttps://doi.org/10.1145/3332466.3374531openalex-snapshot
Overlapping host-to-device copy and computation using hidden unified memory
inferred← citeshttps://doi.org/10.1145/3760386openalex-snapshot
Re-thinking Memory-Bound Limitations in CGRAs
inferred← citeshttps://doi.org/10.5626/jcse.2015.9.2.51openalex-snapshot
Scratchpad Memory Architectures and Allocation Algorithms for Hard Real-Time Multicore Processors
inferred← citeshttps://doi.org/10.7873/date.2013.127openalex-snapshot
Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA
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