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Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/c2013-0-08305-3openalex-snapshot
Computer Organization and Design
inferredcites →https://doi.org/10.1109/2.191995openalex-snapshot
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inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
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inferredcites →https://doi.org/10.1109/aspdac.2009.4796500openalex-snapshot
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inferredcites →https://doi.org/10.1109/date.2004.1269067openalex-snapshot
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inferredcites →https://doi.org/10.1109/date.2005.5openalex-snapshot
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inferredcites →https://doi.org/10.1109/fccm.2004.9openalex-snapshot
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inferredcites →https://doi.org/10.1109/fccm.2009.43openalex-snapshot
Multi-Core Architecture on FPGA for Large Dictionary String Matching
inferredcites →https://doi.org/10.1109/fpl.2005.1515769openalex-snapshot
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inferredcites →https://doi.org/10.1109/fpl.2007.4380625openalex-snapshot
RAMP Blue: A Message-Passing Manycore System in FPGAs
inferredcites →https://doi.org/10.1109/fpl.2007.4380767openalex-snapshot
NoC Implementation in FPGA using Torus Topology
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/icvd.2001.902636openalex-snapshot
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inferredcites →https://doi.org/10.1109/isca.2004.1310774openalex-snapshot
Low-latency virtual-channel routers for on-chip networks
inferredcites →https://doi.org/10.1109/isvlsi.2007.51openalex-snapshot
HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems
inferredcites →https://doi.org/10.1109/mdt.2005.111openalex-snapshot
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research
inferredcites →https://doi.org/10.1109/tc.1985.6312192openalex-snapshot
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inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
inferredcites →https://doi.org/10.1109/vlsisoc.2006.313218openalex-snapshot
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework
inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot
Low-Latency Virtual-Channel Routers for On-Chip Networks
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Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
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Application-aware deadlock-free oblivious routing
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A large scale, homogeneous, fully distributed parallel machine, I
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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inferred← citeshttps://doi.org/10.1109/bec.2016.7743731openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ecmsm.2013.6648932openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ecmsm.2015.7208701openalex-snapshot
Generic GNU/Linux reconfiguration platform proposal
inferred← citeshttps://doi.org/10.1109/euc.2015.18openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/fpl.2013.6645582openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hase.2012.19openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hpec.2014.7040977openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icassp.2013.6638158openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ispass.2012.6189224openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/micro56248.2022.00018openalex-snapshot
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Securing Network-on-chips Against Fault-injection and Crypto-analysis Attacks via Stochastic Anonymous Routing
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MARTHA: architecture for control and emulation of power electronics and smart grid systems
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