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Counter-based cache replacement algorithms
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2000.824338openalex-snapshot
Modified LRU policies for improving second-level cache behavior
inferredcites →https://doi.org/10.1109/hpca.2001.903257openalex-snapshot
Automatically mapping code on an intelligent memory architecture
inferredcites →https://doi.org/10.1109/isca.2001.937453openalex-snapshot
Cache decay: exploiting generational behavior to reduce cache leakage power
inferredcites →https://doi.org/10.1109/pact.1998.727263openalex-snapshot
A direct-execution framework for fast and accurate simulation of superscalar processors
inferredcites →https://doi.org/10.1109/pact.2001.953288openalex-snapshot
Adaptive mode control: a static-power-efficient cache design
inferredcites →https://doi.org/10.1109/pact.2002.1106018openalex-snapshot
Using the compiler to improve cache replacement decisions
inferredcites →https://doi.org/10.1145/1006209.1006213openalex-snapshot
Inter-reference gap distribution replacement
inferredcites →https://doi.org/10.1145/107971.107981openalex-snapshot
A model for estimating trace-sample miss ratios
inferredcites →https://doi.org/10.1145/339647.339669openalex-snapshot
Selective, accurate, and timely self-invalidation using last-touch prediction
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1145/545214.545239openalex-snapshot
Timekeeping in the memory system
inferredcites →https://doi.org/10.1145/944645.944701openalex-snapshot
Tracking object life cycle for leakage energy optimization
inferredcites →https://doi.org/10.1145/944700.944701openalex-snapshot
Tracking object life cycle for leakage energy optimization
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.1147/sj.92.0078openalex-snapshot
Evaluation techniques for storage hierarchies
inferredcites →https://doi.org/10.5555/522344.825699openalex-snapshot
An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors
inferredcites →https://doi.org/10.5555/645989.674328openalex-snapshot
Using the compiler to improve cache replacement decisions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-01721-6openalex-snapshot
Computer Architecture Techniques for Power-Efficiency
inferred← citeshttps://doi.org/10.1007/978-3-319-55345-0_4openalex-snapshot
Reducing Timing Discrepancy for Energy-Efficient On-Chip Memory Architectures at Low-Voltage Mode
inferred← citeshttps://doi.org/10.1007/s11227-012-0859-6openalex-snapshot
Replacement techniques for dynamic NUCA cache designs on CMPs
inferred← citeshttps://doi.org/10.1109/ccece.2007.131openalex-snapshot
Investigating Cache Energy Efficiency in Multimedia Processors
inferred← citeshttps://doi.org/10.1109/dcabes.2012.39openalex-snapshot
An Improved Multi-core Shared Cache Replacement Algorithm
inferred← citeshttps://doi.org/10.1109/hipc.2011.6152739openalex-snapshot
High performance cache block replication using re-reference probability in CMPs
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00050openalex-snapshot
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00048openalex-snapshot
Effective Mimicry of Belady’s MIN Policy
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00055openalex-snapshot
TCOR: A Tile Cache with Optimal Replacement
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071033openalex-snapshot
ACIC: Admission-Controlled Instruction Cache
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00060openalex-snapshot
From Optimal to Practical: Efficient Micro-op Cache Replacement Policies for Data Center Applications
inferred← citeshttps://doi.org/10.1109/iccd.2009.5413142openalex-snapshot
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors
inferred← citeshttps://doi.org/10.1109/iccd.2010.5647608openalex-snapshot
Insertion policy selection using Decision Tree Analysis
inferred← citeshttps://doi.org/10.1109/icenco.2014.7050422openalex-snapshot
Multicore processors: Status quo and future directions
inferred← citeshttps://doi.org/10.1109/icsamos.2009.5289241openalex-snapshot
Instruction-based reuse-distance prediction for effective cache management
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370508openalex-snapshot
Supporting Quality of Service in High-Performance Servers
inferred← citeshttps://doi.org/10.1109/isca.2016.17openalex-snapshot
Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement
inferred← citeshttps://doi.org/10.1109/isca.2018.00020openalex-snapshot
Rethinking Belady's Algorithm to Accommodate Prefetching
inferred← citeshttps://doi.org/10.1109/isca.2018.00057openalex-snapshot
Mitigating Wordline Crosstalk Using Adaptive Trees of Counters
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00063openalex-snapshot
Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00160openalex-snapshot
R-Max: Extending BéLáDy's MIN with Prefetching to Bound Realistic Cache Performance
inferred← citeshttps://doi.org/10.1109/pact.2017.38openalex-snapshot
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries
inferred← citeshttps://doi.org/10.1109/pact58117.2023.00015openalex-snapshot
PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback
inferred← citeshttps://doi.org/10.1109/pact58117.2023.00019openalex-snapshot
Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs
inferred← citeshttps://doi.org/10.1109/tc.2013.61openalex-snapshot
LACS: A Locality-Aware Cost-Sensitive Cache Replacement Algorithm
inferred← citeshttps://doi.org/10.1109/trustcom.2013.139openalex-snapshot
Combining Process-Based Cache Partitioning and Pollute Region Isolation to Improve Shared Last Level Cache Utilization on Multicore Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2420954openalex-snapshot
Sequoia: A High-Endurance NVM-Based Cache Architecture
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2642170openalex-snapshot
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
inferred← citeshttps://doi.org/10.1145/1166133.1166135openalex-snapshot
Investigating cache energy and latency break-even points in high performance processors
inferred← citeshttps://doi.org/10.1145/1166133.1166139openalex-snapshot
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches
inferred← citeshttps://doi.org/10.1145/1327312.1327316openalex-snapshot
Investigating cache energy and latency break-even points in high performance processors
inferred← citeshttps://doi.org/10.1145/1327312.1327320openalex-snapshot
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches
inferred← citeshttps://doi.org/10.1145/1787275.1787316openalex-snapshot
Where replacement algorithms fail
inferred← citeshttps://doi.org/10.1145/2019608.2019613openalex-snapshot
Dynamic access distance driven cache replacement
inferred← citeshttps://doi.org/10.1145/3168819openalex-snapshot
Lightweight detection of cache conflicts
inferred← citeshttps://doi.org/10.1145/3179541.3168819openalex-snapshot
Lightweight detection of cache conflicts
inferred← citeshttps://doi.org/10.1145/3185089.3185124openalex-snapshot
Evaluation of Misspeculation Impact on Chip-Multiprocessors Power Overhead
inferred← citeshttps://doi.org/10.1145/3352460.3358319openalex-snapshot
Applying Deep Learning to the Cache Replacement Problem
inferred← citeshttps://doi.org/10.1145/3620666.3651353openalex-snapshot
GMT: GPU Orchestrated Memory Tiering for the Big Data Era
inferred← citeshttps://doi.org/10.1145/3694715.3695953openalex-snapshot
BIZA: Design of Self-Governing Block-Interface ZNS AFA for Endurance and Performance
inferred← citeshttps://doi.org/10.2200/s00922ed1v01y201905cac047openalex-snapshot
Cache Replacement Policies
inferred← citeshttps://doi.org/10.48550/arxiv.1001.4135openalex-snapshot
An Adaptive Dynamic Replacement Approach for a Multicast based Popularity Aware Prefix Cache Memory System
inferred← citeshttps://doi.org/10.5075/epfl-thesis-6631openalex-snapshot
Multi-Gigabyte On-Chip DRAM Caches for Servers
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94560openalex-snapshot
Managing dynamic non-uiform cache architectures
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