On the public citation graph
Using the compiler to improve cache replacement decisions
0 signed · 125 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44520-x_31openalex-snapshot
Load Scheduling with Profile Information
inferredcites →https://doi.org/10.1109/12.752656openalex-snapshot
An algorithm for optimally exploiting spatial and temporal locality in upper memory levels
inferredcites →https://doi.org/10.1109/2.689677openalex-snapshot
Smarter memory: improving bandwidth for streamed references
inferredcites →https://doi.org/10.1109/71.86110openalex-snapshot
An implementation of interprocedural bounded regular section analysis
inferredcites →https://doi.org/10.1109/hpca.2000.824338openalex-snapshot
Modified LRU policies for improving second-level cache behavior
inferredcites →https://doi.org/10.1109/hpca.2001.903272openalex-snapshot
Reducing DRAM latencies with an integrated memory hierarchy design
inferredcites →https://doi.org/10.1109/iccd.1998.727028openalex-snapshot
The Alpha 21264 microprocessor architecture
inferredcites →https://doi.org/10.1145/125826.125932openalex-snapshot
An effective on-chip preloading scheme to reduce data access penalty
inferredcites →https://doi.org/10.1145/135226.135233openalex-snapshot
A practical algorithm for exact array dependence analysis
inferredcites →https://doi.org/10.1145/143365.143488openalex-snapshot
Design and evaluation of a compiler algorithm for prefetching
inferredcites →https://doi.org/10.1145/166955.166974openalex-snapshot
Efficient simulation of caches under optimal replacement with applications to miss characterization
inferredcites →https://doi.org/10.1145/191995.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferredcites →https://doi.org/10.1145/233561.233564openalex-snapshot
Improving data locality with loop transformations
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/277830.277941openalex-snapshot
Utilizing reuse information in data cache management
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/291069.291051openalex-snapshot
Precise miss analysis for program transformations with caches of arbitrary associativity
inferredcites →https://doi.org/10.1145/329466.329484openalex-snapshot
Quantifying loop nest locality using SPEC'95 and the perfect benchmarks
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.5555/266800.266806openalex-snapshot
Run-time spatial locality detection and optimization
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11859802_7openalex-snapshot
A Study of the Performance Potential for Dynamic Instruction Hints Selection
inferred← citeshttps://doi.org/10.1007/978-0-387-74935-8_32openalex-snapshot
A Simulation-Based Study on Memory Design Issues for Embedded Systems
inferred← citeshttps://doi.org/10.1007/978-3-030-72789-5_7openalex-snapshot
CLAM: Compiler Leasing of Accelerator Memory
inferred← citeshttps://doi.org/10.1007/978-3-540-24644-2_6openalex-snapshot
Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation
inferred← citeshttps://doi.org/10.1007/978-3-540-30102-8_4openalex-snapshot
Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy
inferred← citeshttps://doi.org/10.1007/978-3-540-89740-8_15openalex-snapshot
P-OPT: Program-Directed Optimal Cache Management
inferred← citeshttps://doi.org/10.1007/s10766-005-7304-xopenalex-snapshot
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.05.005openalex-snapshot
A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines
inferred← citeshttps://doi.org/10.1016/j.sysarc.2004.09.004openalex-snapshot
Generating cache hints for improved program efficiency
inferred← citeshttps://doi.org/10.1109/ccece.2007.131openalex-snapshot
Investigating Cache Energy Efficiency in Multimedia Processors
inferred← citeshttps://doi.org/10.1109/cit.2005.3openalex-snapshot
A compiler-controlled instruction cache architecture for an embedded low power microprocessor
inferred← citeshttps://doi.org/10.1109/discover.2016.7806218openalex-snapshot
A survey on replacement strategies in cache memory for embedded systems
inferred← citeshttps://doi.org/10.1109/hipc.2009.5433214openalex-snapshot
Cache streamization for high performance stream processor
inferred← citeshttps://doi.org/10.1109/hpca.2007.346181openalex-snapshot
Evaluating MapReduce for Multi-core and Multiprocessor Systems
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446101openalex-snapshot
RADAR: Runtime-assisted dead region management for last-level caches
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00028openalex-snapshot
Domain-Specialized Cache Management for Graph Analytics
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00050openalex-snapshot
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
inferred← citeshttps://doi.org/10.1109/icaee48663.2019.8975563openalex-snapshot
Performance Analysis of Cache Size and Set-Associativity using simpleScalar Benchmark
inferred← citeshttps://doi.org/10.1109/icasic.2005.1611276openalex-snapshot
Codes Reallocation and Prediction For Power Efficiency in I-Cache Memory
inferred← citeshttps://doi.org/10.1109/iccad.2013.6691165openalex-snapshot
An efficient compiler framework for cache bypassing on GPUs
inferred← citeshttps://doi.org/10.1109/iccd.2005.41openalex-snapshot
Counter-based cache replacement algorithms
inferred← citeshttps://doi.org/10.1109/icpp.2003.1240591openalex-snapshot
A hardware-based cache pollution filtering mechanism for aggressive prefetches
inferred← citeshttps://doi.org/10.1109/iiswc.2013.6704685openalex-snapshot
Platform-independent analysis of function-level communication in workloads
inferred← citeshttps://doi.org/10.1109/interact.2005.7openalex-snapshot
Cooperative Caching with Keep-Me and Evict-Me
inferred← citeshttps://doi.org/10.1109/interact.2012.6339621openalex-snapshot
Enhancing LRU replacement via phantom associativity
inferred← citeshttps://doi.org/10.1109/isca.2018.00020openalex-snapshot
Rethinking Belady's Algorithm to Accommodate Prefetching
inferred← citeshttps://doi.org/10.1109/isca.2018.00027openalex-snapshot
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory
inferred← citeshttps://doi.org/10.1109/isca.2018.00050openalex-snapshot
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer
inferred← citeshttps://doi.org/10.1109/isorc.2015.12openalex-snapshot
Real-Time GPU Computing: Cache or No Cache?
inferred← citeshttps://doi.org/10.1109/itng.2007.150openalex-snapshot
Performance Evaluation of Cache Memory Organizations in Embedded Systems
inferred← citeshttps://doi.org/10.1109/mic.2020.3026245openalex-snapshot
Rethinking Divide and Conquer—Towards Holistic Interfaces of the Computing Stack
inferred← citeshttps://doi.org/10.1109/micro.2008.4771793openalex-snapshot
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
inferred← citeshttps://doi.org/10.1109/micro.2010.24openalex-snapshot
Sampling Dead Block Prediction for Last-Level Caches
inferred← citeshttps://doi.org/10.1109/mtdt.2004.1327979openalex-snapshot
SF-LRU cache replacement algorithm
inferred← citeshttps://doi.org/10.1109/pact.2009.35openalex-snapshot
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
inferred← citeshttps://doi.org/10.1109/pact.2011.50openalex-snapshot
Collaborative Caching for Unknown Cache Sizes
inferred← citeshttps://doi.org/10.1109/sbac-pad.2004.11openalex-snapshot
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance
inferred← citeshttps://doi.org/10.1109/sc.2010.44openalex-snapshot
Reducing Cache Pollution Through Detection and Elimination of Non-Temporal Memory Accesses
inferred← citeshttps://doi.org/10.1109/sips.2005.1579932openalex-snapshot
An improved instruction cache replacement algorithm
inferred← citeshttps://doi.org/10.1109/socc.2010.5784682openalex-snapshot
Way-load balancing scheme for mobile cache LRU replacement
inferred← citeshttps://doi.org/10.1109/ssst.2003.1194606openalex-snapshot
A performance evaluation of memory hierarchy in embedded systems
inferred← citeshttps://doi.org/10.1109/tc.2007.17openalex-snapshot
Reducing Cache Pollution via Dynamic Data Prefetch Filtering
inferred← citeshttps://doi.org/10.1109/tc.2007.70816openalex-snapshot
Counter-Based Cache Replacement and Bypassing Algorithms
inferred← citeshttps://doi.org/10.1109/tc.2015.2395435openalex-snapshot
GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs
inferred← citeshttps://doi.org/10.1109/vdat50263.2020.9190377openalex-snapshot
Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA
inferred← citeshttps://doi.org/10.1145/1166133.1166135openalex-snapshot
Investigating cache energy and latency break-even points in high performance processors
inferred← citeshttps://doi.org/10.1145/1166133.1166139openalex-snapshot
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches
inferred← citeshttps://doi.org/10.1145/1250662.1250707openalex-snapshot
Comparing memory systems for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferred← citeshttps://doi.org/10.1145/1327312.1327316openalex-snapshot
Investigating cache energy and latency break-even points in high performance processors
inferred← citeshttps://doi.org/10.1145/1455650.1455651openalex-snapshot
Comparative evaluation of memory models for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1639949.1640101openalex-snapshot
A concurrent dynamic analysis framework for multicore hardware
inferred← citeshttps://doi.org/10.1145/1640089.1640101openalex-snapshot
A concurrent dynamic analysis framework for multicore hardware
inferred← citeshttps://doi.org/10.1145/1854273.1854333openalex-snapshot
Using dead blocks as a virtual victim cache
inferred← citeshttps://doi.org/10.1145/1988915.1988927openalex-snapshot
Minor memory references matter in collaborative caching
inferred← citeshttps://doi.org/10.1145/1993478.1993485openalex-snapshot
On the theory and potential of LRU-MRU collaborative cache management
inferred← citeshttps://doi.org/10.1145/2019608.2019613openalex-snapshot
Dynamic access distance driven cache replacement
inferred← citeshttps://doi.org/10.1145/2076022.1993485openalex-snapshot
On the theory and potential of LRU-MRU collaborative cache management
inferred← citeshttps://doi.org/10.1145/2159430.2159443openalex-snapshot
Reducing off-chip memory traffic by selective cache management scheme in GPGPUs
inferred← citeshttps://doi.org/10.1145/2258996.2259012openalex-snapshot
A generalized theory of collaborative caching
inferred← citeshttps://doi.org/10.1145/2426642.2259012openalex-snapshot
A generalized theory of collaborative caching
inferred← citeshttps://doi.org/10.1145/2464996.2465443openalex-snapshot
Prefetching and cache management using task lifetimes
inferred← citeshttps://doi.org/10.1145/2492408.2492422openalex-snapshot
Cache rationing for multicore
inferred← citeshttps://doi.org/10.1145/2503210.2503224openalex-snapshot
Location-aware cache management for many-core processors with deep cache hierarchy
inferred← citeshttps://doi.org/10.1145/2628071.2628120openalex-snapshot
Protection and utilization in shared cache through rationing
inferred← citeshttps://doi.org/10.1145/2807591.2807625openalex-snapshot
Runtime-driven shared last-level cache management for task-parallel programs
inferred← citeshttps://doi.org/10.1145/2926697.2926705openalex-snapshot
Hardware support for protective and collaborative cache sharing
inferred← citeshttps://doi.org/10.1145/3234337openalex-snapshot
Global Dead-Block Management for Task-Parallel Programs
inferred← citeshttps://doi.org/10.1145/3241624.2926705openalex-snapshot
Hardware support for protective and collaborative cache sharing
inferred← citeshttps://doi.org/10.1145/3297858.3304067openalex-snapshot
Beating OPT with Statistical Clairvoyance and Variable Size Caching
inferred← citeshttps://doi.org/10.1145/3422575.3422800openalex-snapshot
CLAM: Compiler Lease of Cache Memory
inferred← citeshttps://doi.org/10.1145/3459898.3463908openalex-snapshot
Uniform lease vs. LRU cache: analysis and evaluation
inferred← citeshttps://doi.org/10.1145/3498730openalex-snapshot
CARL: Compiler Assigned Reference Leasing
inferred← citeshttps://doi.org/10.1145/3505250openalex-snapshot
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations
inferred← citeshttps://doi.org/10.1145/3530819openalex-snapshot
A Case for Fine-grain Coherence Specialization in Heterogeneous Systems
inferred← citeshttps://doi.org/10.1145/3631882.3631892openalex-snapshot
E=MC^2: Efficient Mobility Centric Caching
inferred← citeshttps://doi.org/10.1145/3767110.3767126openalex-snapshot
Benchmarking Cache Programming Against Optimal Caching
inferred← citeshttps://doi.org/10.1145/986537.986601openalex-snapshot
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite
inferred← citeshttps://doi.org/10.14257/astl.2014.46.06openalex-snapshot
A Novel Last-level Cache Replacement Policy to Improve the Performance of Mobile Systems
inferred← citeshttps://doi.org/10.14569/ijacsa.2017.080118openalex-snapshot
A Computationally Efficient P-LRU based Optimal Cache Heap Object Replacement Policy
inferred← citeshttps://doi.org/10.17760/d20382826openalex-snapshot
Hint-assisted scheduling on modern GPUs
inferred← citeshttps://doi.org/10.22581/muet1982.1704.08openalex-snapshot
Cache Memory: An Analysis on Replacement Algorithms and Optimization Techniques
inferred← citeshttps://doi.org/10.31274/rtd-180813-16995openalex-snapshot
Performance analysis and optimization of the Java memory system
inferred← citeshttps://doi.org/10.3233/emc-2005-00048openalex-snapshot
Improving power efficiency with compiler-assisted cache replacement
inferred← citeshttps://doi.org/10.4304/jcp.5.2.242-249openalex-snapshot
Optimizing the Management of Reference Prediction Table for Prefetching and Prepromotion
inferred← citeshttps://doi.org/10.5821/dissertation-2117-335422openalex-snapshot
Runtime-assisted optimizations in the on-chip memory hierarchy
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.