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Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/jagm.1997.0898openalex-snapshot
Isomorph-Free Exhaustive Generation
inferredcites →https://doi.org/10.1109/43.924826openalex-snapshot
Low-power system-level design of VLSI packet switching fabrics
inferredcites →https://doi.org/10.1109/conect.2003.1231471openalex-snapshot
A wave-pipelined on-chip interconnect structure for networks-on-chips
inferredcites →https://doi.org/10.1109/dac.2002.1012681openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1109/date.2004.1269002openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.1109/date.2004.1269067openalex-snapshot
A power and performance model for network-on-chip architectures
inferredcites →https://doi.org/10.1109/date.2005.40openalex-snapshot
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
inferredcites →https://doi.org/10.1109/iccd.2002.1106743openalex-snapshot
Physical planning of on-chip interconnect architectures
inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot
A network on chip architecture and design methodology
inferredcites →https://doi.org/10.1109/jssc.2003.810060openalex-snapshot
Near speed-of-light signaling over on-chip electrical interconnects
inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/378239.379047openalex-snapshot
On-chip communication architecture for OC-768 network processors
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-981-10-1023-1_50openalex-snapshot
Design and Testing of Low Power Reliable NoCs for Wireless Applications
inferred← citeshttps://doi.org/10.1016/j.micpro.2009.03.002openalex-snapshot
Power optimization for application-specific networks-on-chips: A topology-based approach
inferred← citeshttps://doi.org/10.1016/j.vlsi.2010.02.003openalex-snapshot
A low-overhead and reliable switch architecture for Network-on-Chips
inferred← citeshttps://doi.org/10.1109/aspdac.2008.4483953openalex-snapshot
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks
inferred← citeshttps://doi.org/10.1109/cicsyn.2015.41openalex-snapshot
Heterogeneous and Hybrid Clustered Topology for Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/dac.2006.229293openalex-snapshot
Communication latency aware low power NoC synthesis
inferred← citeshttps://doi.org/10.1109/iccad.2008.4681630openalex-snapshot
Advancing supercomputer performance through interconnection topology synthesis
inferred← citeshttps://doi.org/10.1109/iccd.2006.4380807openalex-snapshot
A Performance and Power Analysis of WK-Recursive and Mesh Networks for Network-on-Chips
inferred← citeshttps://doi.org/10.1109/icpads.2007.4447766openalex-snapshot
Effect of number of faults on NoC power and performance
inferred← citeshttps://doi.org/10.1109/iscas.2008.4541429openalex-snapshot
Power-aware topology optimization for networks-on-chips
inferred← citeshttps://doi.org/10.1109/isqed.2013.6523678openalex-snapshot
Reliability-aware and energy-efficient synthesis of NoC based MPSoCs
inferred← citeshttps://doi.org/10.1109/reconfig.2009.48openalex-snapshot
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips
inferred← citeshttps://doi.org/10.1109/tcad.2009.2013273openalex-snapshot
A Methodology for Constraint-Driven Synthesis of On-Chip Communications
inferred← citeshttps://doi.org/10.1109/tvlsi.2012.2195688openalex-snapshot
CusNoC: Fast Full-Chip Custom NoC Generation
inferred← citeshttps://doi.org/10.1145/1146909.1147058openalex-snapshot
Communication latency aware low power NoC synthesis
inferred← citeshttps://doi.org/10.1145/1455229.1455242openalex-snapshot
Energy and switch area optimizations for FPGA global routing architectures
inferred← citeshttps://doi.org/10.1145/2159542.2159544openalex-snapshot
Optimized 3D Network-on-Chip Design Using Simulated Allocation
inferred← citeshttps://doi.org/10.1201/9781315216072openalex-snapshot
Network-on-Chip: The Next Generation of System-on-Chip Integration
inferred← citeshttps://doi.org/10.1201/9781315216072-9openalex-snapshot
Application-Specific Network-on-Chip Synthesis
inferred← citeshttps://doi.org/10.1201/b17748-10openalex-snapshot
Application-Specific Network- on-Chip Synthesis
inferred← citeshttps://doi.org/10.34917/1945265openalex-snapshot
Parameterizable network-on-chip emulation framework
inferred← citeshttps://doi.org/10.4108/icst.nanonet2007.2148openalex-snapshot
Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support
inferred← citeshttps://doi.org/10.5555/1356802.1356869openalex-snapshot
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
inferred← citeshttps://doi.org/10.5555/1509456.1509579openalex-snapshot
Advancing supercomputer performance through interconnection topology synthesis
inferred← citeshttps://doi.org/10.7763/ijcee.2011.v3.329openalex-snapshot
Network-on-Chip: Power Optimization Architecture Mapping based on Global Interconnection Links
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