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A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.83652openalex-snapshot
Express cubes: improving the performance of k-ary n-cube interconnection networks
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
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Mesh routing topologies for multi-FPGA systems
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Analysis of power consumption on switch fabrics in network routers
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A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1109/date.2004.1268999openalex-snapshot
×pipesCompiler: a tool for instantiating application specific networks on chip
inferredcites →https://doi.org/10.1109/hpca.1997.569611openalex-snapshot
The impact of instruction-level parallelism on multiprocessor performance and simulation methodology
inferredcites →https://doi.org/10.1109/hpca.2003.1183551openalex-snapshot
Scalar operand networks: on-chip interconnect for ILP in partitioned architectures
inferredcites →https://doi.org/10.1109/iwv.1999.760456openalex-snapshot
Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/micro.2003.1253187openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.1109/tc.1985.6312192openalex-snapshot
Fat-trees: Universal networks for hardware-efficient supercomputing
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.1145/859618.859667openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.5555/968879.969208openalex-snapshot
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A Routing Methodology for Dynamic Fault Tolerance in Meshes and Tori
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Packet-based Adaptive Virtual Channel Configuration for NoC Systems
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High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area
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Reconfigurable on-chip interconnection networks for high performance embedded SoC design
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Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
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Prediction router: Yet another low latency on-chip router architecture
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Implementation and Evaluation of Large Interconnection Routers for Future Many-core Networks on Chip
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Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
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Throttling Control for Bufferless Routing in On-chip Networks
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ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
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Area and Power Modeling Methodologies for Networks-on-Chip
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Modeling and Evaluation of an Energy-Efficient Hierarchical Ring Interconnect for System-on-Chip Multiprocessors
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NoC Design and Implementation in 65nm Technology
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Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework
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Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy Estimation
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Quantitative Comparison of Switching Strategies for Networks on Chip
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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
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Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes
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Communication latency aware low power NoC synthesis
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A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
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Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
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Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review
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Energy efficient multiprocessor task scheduling under input-dependent variation
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