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Contention-aware application mapping for Network-on-Chip communication architectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-78240-4openalex-snapshot
Geometric Algorithms and Combinatorial Optimization
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Geometric Algorithms and Combinatorial Optimization
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Codex-dp: co-design of communicating systems using dynamic programming
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Analysis of power consumption on switch fabrics in network routers
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Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.1109/date.2006.243837openalex-snapshot
optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs
inferredcites →https://doi.org/10.1109/date.2007.364415openalex-snapshot
Congestion-Controlled Best-Effort Communication for Networks-on-Chip
inferredcites →https://doi.org/10.1109/dsd.2003.1231923openalex-snapshot
A two-step genetic algorithm for mapping task graphs to a network on chip architecture
inferredcites →https://doi.org/10.1109/eurdac.1996.558204openalex-snapshot
MILP based task mapping for heterogeneous multiprocessor systems
inferredcites →https://doi.org/10.1109/iccd.2004.1347957openalex-snapshot
Linear programming based techniques for synthesis of network-on-chip architectures
inferredcites →https://doi.org/10.1109/iccd.2004.1347959openalex-snapshot
Many-to-many core-switch mapping in 2-D mesh NoC architectures
inferredcites →https://doi.org/10.1109/icppw.2001.951976openalex-snapshot
Comparison of contention aware list scheduling heuristics for cluster computing
inferredcites →https://doi.org/10.1109/lpe.2005.195552openalex-snapshot
A technique for low energy mapping and routing in network-on-chip architectures
inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot
Energy- and performance-aware mapping for regular NoC architectures
inferredcites →https://doi.org/10.1109/tpds.2005.64openalex-snapshot
Communication contention in task scheduling
inferredcites →https://doi.org/10.1145/1016720.1016765openalex-snapshot
Multi-objective mapping for mesh-based NoC architectures
inferredcites →https://doi.org/10.1145/1077603.1077695openalex-snapshot
A technique for low energy mapping and routing in network-on-chip architectures
inferredcites →https://doi.org/10.1145/1084834.1084857openalex-snapshot
A unified approach to constrained mapping and routing on network-on-chip architectures
inferredcites →https://doi.org/10.1145/1255456.1255460openalex-snapshot
On-chip communication architecture exploration
inferredcites →https://doi.org/10.1145/1283780.1283871openalex-snapshot
An ilp based approach to reducing energy consumption in nocbased CMPS
inferredcites →https://doi.org/10.1145/513918.514051openalex-snapshot
Analysis of power consumption on switch fabrics in network routers
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Architecture aware semi partitioned real-time scheduling on multicore platforms
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Analysis of Approaches for Synthesis of Networks-on-chip by Using Circulant Topologies
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Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip
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Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems
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Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip
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Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design
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Neighborhood-aware data locality optimization for NoC-based multicores
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Congestion-aware scheduling for NoC-based reconfigurable systems
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A Greedy Heuristic for Process Mapping on Networks-on-Chip
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Practical strategies to monitor and control contention in shared resources of critical real-time embedded systems
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Worst-case delay analysis of core-to-IO flows over many-cores architectures
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