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Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/spe.2796openalex-snapshot
An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication
inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_11openalex-snapshot
Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures
inferredcites →https://doi.org/10.1007/978-3-030-31310-4openalex-snapshot
Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures
inferredcites →https://doi.org/10.1007/978-3-319-93073-2_6openalex-snapshot
Particle Swarm Optimization
inferredcites →https://doi.org/10.1007/s10489-018-1246-7openalex-snapshot
An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks
inferredcites →https://doi.org/10.1007/s10836-017-5646-0openalex-snapshot
Link Testing: a Survey of Current Trends in Network on Chip
inferredcites →https://doi.org/10.1007/s11036-019-01356-xopenalex-snapshot
A Hybrid Task Scheduling Algorithm Based on Task Clustering
inferredcites →https://doi.org/10.1007/s11227-014-1348-xopenalex-snapshot
Application mapping algorithms for mesh-based network-on-chip architectures
inferredcites →https://doi.org/10.1007/s11227-016-1746-3openalex-snapshot
Application mapping onto mesh-based network-on-chip using constructive heuristic algorithms
inferredcites →https://doi.org/10.1007/s11227-018-2248-2openalex-snapshot
HYSTERY: a hybrid scheduling and mapping approach to optimize temperature, energy consumption and lifetime reliability of heterogeneous multiprocessor systems
inferredcites →https://doi.org/10.1016/j.advengsoft.2011.06.005openalex-snapshot
Cluster-based application mapping method for Network-on-Chip
inferredcites →https://doi.org/10.1016/j.micpro.2017.09.004openalex-snapshot
Application mapping to mesh NoCs using a Tabu-search based swarm optimization
inferredcites →https://doi.org/10.1016/j.micpro.2018.10.008openalex-snapshot
Energy efficient heuristic application mapping for 2-D mesh-based network-on-chip
inferredcites →https://doi.org/10.1016/j.protcy.2016.08.138openalex-snapshot
Cluster Based Application Mapping Strategy for 2D NoC
inferredcites →https://doi.org/10.1016/j.sysarc.2007.07.004openalex-snapshot
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip
inferredcites →https://doi.org/10.1016/j.sysarc.2010.04.007openalex-snapshot
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
inferredcites →https://doi.org/10.1016/j.sysarc.2010.10.001openalex-snapshot
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
inferredcites →https://doi.org/10.1016/j.sysarc.2012.10.004openalex-snapshot
A survey on application mapping strategies for Network-on-Chip design
inferredcites →https://doi.org/10.1016/j.sysarc.2018.08.002openalex-snapshot
Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip
inferredcites →https://doi.org/10.1016/j.sysarc.2018.10.001openalex-snapshot
A survey on fault-tolerant application mapping techniques for Network-on-Chip
inferredcites →https://doi.org/10.1016/j.vlsi.2018.02.002openalex-snapshot
Reliability-aware application mapping onto mesh based Network-on-Chip
inferredcites →https://doi.org/10.1049/iet-cdt.2018.5055openalex-snapshot
KBMA: A knowledge‐based multi‐objective application mapping approach for 3D NoC
inferredcites →https://doi.org/10.1049/ip-cdt:20045092openalex-snapshot
Communication and task scheduling of application-specific networks-on-chip
inferredcites →https://doi.org/10.1049/ip-cdt:20045155openalex-snapshot
Efficient reverse converters for four-moduli sets { 2n−1, 2n, 2n+1, 2n+1−1} and {2n−1, 2n, 2n+1, 2n−1−1}
inferredcites →https://doi.org/10.1080/17445760.2017.1399206openalex-snapshot
A Cross-layer based mapping for spiking neural network onto network on chip
inferredcites →https://doi.org/10.1109/access.2017.2778340openalex-snapshot
Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture
inferredcites →https://doi.org/10.1109/access.2018.2811716openalex-snapshot
An Efficient Algorithm for Mapping Real Time Embedded Applications on NoC Architecture
inferredcites →https://doi.org/10.1109/access.2019.2944490openalex-snapshot
Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router
inferredcites →https://doi.org/10.1109/asicon.2015.7516953openalex-snapshot
An inclusive fault model for Network-on-Chip
inferredcites →https://doi.org/10.1109/aspdac.2005.1466124openalex-snapshot
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
inferredcites →https://doi.org/10.1109/aspdac.2018.8297296openalex-snapshot
Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems
inferredcites →https://doi.org/10.1109/date.2004.1269002openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.1109/date.2006.243952openalex-snapshot
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study
inferredcites →https://doi.org/10.1109/date.2006.244069openalex-snapshot
Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs
inferredcites →https://doi.org/10.1109/date.2007.364415openalex-snapshot
Congestion-Controlled Best-Effort Communication for Networks-on-Chip
inferredcites →https://doi.org/10.1109/date.2007.364574openalex-snapshot
An ILP Formulation for System-Level Application Mapping on Network Processor Architectures
inferredcites →https://doi.org/10.1109/date.2009.5090700openalex-snapshot
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
inferredcites →https://doi.org/10.1109/ddecs.2008.4538763openalex-snapshot
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
inferredcites →https://doi.org/10.1109/depend.2010.25openalex-snapshot
RMAP: A Reliability-Aware Application Mapping for Network-on-Chips
inferredcites →https://doi.org/10.1109/dsd.2003.1231923openalex-snapshot
A two-step genetic algorithm for mapping task graphs to a network on chip architecture
inferredcites →https://doi.org/10.1109/dsd.2009.145openalex-snapshot
Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms
inferredcites →https://doi.org/10.1109/dtis.2006.1708657openalex-snapshot
An application specific NoC mapping for optimized delay
inferredcites →https://doi.org/10.1109/dtis.2017.7929873openalex-snapshot
Run-time resource allocation for embedded Multiprocessor System-on-Chip using tree-based design space exploration
inferredcites →https://doi.org/10.1109/empdp.2000.823437openalex-snapshot
An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures
inferredcites →https://doi.org/10.1109/eurdac.1996.558204openalex-snapshot
MILP based task mapping for heterogeneous multiprocessor systems
inferredcites →https://doi.org/10.1109/icaict.2009.5372524openalex-snapshot
An ILP formulation for application mapping onto Network-on-Chips
inferredcites →https://doi.org/10.1109/iccad.2017.8203781openalex-snapshot
A load balancing inspired optimization framework for exascale multicore systems: A complex networks approach
inferredcites →https://doi.org/10.1109/iccd.2004.1347957openalex-snapshot
Linear programming based techniques for synthesis of network-on-chip architectures
inferredcites →https://doi.org/10.1109/iccd.2004.1347959openalex-snapshot
Many-to-many core-switch mapping in 2-D mesh NoC architectures
inferredcites →https://doi.org/10.1109/iccd.2008.4751856openalex-snapshot
Contention-aware application mapping for Network-on-Chip communication architectures
inferredcites →https://doi.org/10.1109/iccd.2012.6378665openalex-snapshot
CoNA: Dynamic application mapping for congestion reduction in many-core systems
inferredcites →https://doi.org/10.1109/iccrd.2011.5764225openalex-snapshot
Energy and thermal aware mapping for mesh-based NoC architectures using multi-objective ant colony algorithm
inferredcites →https://doi.org/10.1109/ikt.2016.7777757openalex-snapshot
RASMAP: An efficient heuristic application mapping algorithm for network-on-chips
inferredcites →https://doi.org/10.1109/indcon.2010.5712700openalex-snapshot
A new application mapping algorithm for mesh based Network-on-Chip design
inferredcites →https://doi.org/10.1109/iscas.2017.8050254openalex-snapshot
Dark silicon-power-thermal aware runtime mapping and configuration in heterogeneous many-core NoC
inferredcites →https://doi.org/10.1109/iscas.2018.8351580openalex-snapshot
Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era
inferredcites →https://doi.org/10.1109/ised.2012.17openalex-snapshot
Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization
inferredcites →https://doi.org/10.1109/isscs.2007.4292678openalex-snapshot
SMAP: An Intelligent Mapping tool for Network on Chip
inferredcites →https://doi.org/10.1109/issoc.2008.4694878openalex-snapshot
Congestion-aware task mapping in heterogeneous MPSoCs
inferredcites →https://doi.org/10.1109/istel.2016.7881908openalex-snapshot
XY-axis and distance based NoC mapping (XY-ADB)
inferredcites →https://doi.org/10.1109/isvlsi.2011.21openalex-snapshot
Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization
inferredcites →https://doi.org/10.1109/les.2015.2427571openalex-snapshot
WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems
inferredcites →https://doi.org/10.1109/mcsoc2018.2018.00038openalex-snapshot
On the Complexity of Mapping Feasibility in Many-Core Architectures
inferredcites →https://doi.org/10.1109/mdt.2005.108openalex-snapshot
Design, Synthesis, and Test of Networks on Chips
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/mm.2003.1225959openalex-snapshot
Trends and challenges in VLSI circuit reliability
inferredcites →https://doi.org/10.1109/newcas.2005.1496682openalex-snapshot
Adaptive Scheduling for CDMA-Based-Networks-on-Chip
inferredcites →https://doi.org/10.1109/nocarc.2018.8541173openalex-snapshot
NN-Noxim: High-Level Cycle-Accurate NoC-based Neural Networks Simulator
inferredcites →https://doi.org/10.1109/nocarc.2018.8541206openalex-snapshot
Hierarchical and Dependency-Aware Task Mapping for NoC-based Systems
inferredcites →https://doi.org/10.1109/nocs.2007.5openalex-snapshot
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network
inferredcites →https://doi.org/10.1109/nocs.2009.5071448openalex-snapshot
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels
inferredcites →https://doi.org/10.1109/nocs.2014.7008757openalex-snapshot
An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms
inferredcites →https://doi.org/10.1109/pdp.2011.10openalex-snapshot
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
inferredcites →https://doi.org/10.1109/pdp.2014.100openalex-snapshot
Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems
inferredcites →https://doi.org/10.1109/rsp.2007.26openalex-snapshot
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
inferredcites →https://doi.org/10.1109/sips.2008.4671762openalex-snapshot
Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks
inferredcites →https://doi.org/10.1109/tcad.2008.2003301openalex-snapshot
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
inferredcites →https://doi.org/10.1109/tcad.2008.2010691openalex-snapshot
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
inferredcites →https://doi.org/10.1109/tpds.2019.2921542openalex-snapshot
On Runtime Communication and Thermal-Aware Application Mapping and Defragmentation in 3D NoC Systems
inferredcites →https://doi.org/10.1109/tvlsi.2019.2897650openalex-snapshot
Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach
inferredcites →https://doi.org/10.1109/vlsid.2019.00119openalex-snapshot
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture
inferredcites →https://doi.org/10.1142/s0218126615501261openalex-snapshot
A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip
inferredcites →https://doi.org/10.1145/1077603.1077695openalex-snapshot
A technique for low energy mapping and routing in network-on-chip architectures
inferredcites →https://doi.org/10.1145/1084834.1084856openalex-snapshot
Key research problems in NoC design
inferredcites →https://doi.org/10.1145/1084834.1084857openalex-snapshot
A unified approach to constrained mapping and routing on network-on-chip architectures
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/1132952.1132953openalex-snapshot
A survey of research and practices of Network-on-chip
inferredcites →https://doi.org/10.1145/1176254.1176268openalex-snapshot
Automatic run-time extraction of communication graphs from multithreaded applications
inferredcites →https://doi.org/10.1145/1254766.1254796openalex-snapshot
Compiler-directed application mapping for NoC based chip multiprocessors
inferredcites →https://doi.org/10.1145/1273444.1254796openalex-snapshot
Compiler-directed application mapping for NoC based chip multiprocessors
inferredcites →https://doi.org/10.1145/1283780.1283871openalex-snapshot
An ilp based approach to reducing energy consumption in nocbased CMPS
inferredcites →https://doi.org/10.1145/1289816.1289824openalex-snapshot
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules
inferredcites →https://doi.org/10.1145/1403375.1403675openalex-snapshot
User-aware dynamic task allocation in networks-on-chip
inferredcites →https://doi.org/10.1145/2463209.2488734openalex-snapshot
Mapping on multi/many-core systems
inferredcites →https://doi.org/10.1145/2463209.2488782openalex-snapshot
Smart hill climbing for agile dynamic mapping in many-core systems
inferredcites →https://doi.org/10.1145/2522968.2522976openalex-snapshot
Methods for fault tolerance in networks-on-chip
inferredcites →https://doi.org/10.1145/2656106.2656111openalex-snapshot
A system-level simulation framework for evaluating task migration in MPSoCs
inferredcites →https://doi.org/10.1145/2786572.2786575openalex-snapshot
User Cooperation Network Coding Approach for NoC Performance Improvement
inferredcites →https://doi.org/10.1145/2892633openalex-snapshot
Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip
inferredcites →https://doi.org/10.1145/2968456.2968471openalex-snapshot
Scalable and realistic benchmark synthesis for efficient NoC performance evaluation
inferredcites →https://doi.org/10.1145/3182173openalex-snapshot
A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores
inferredcites →https://doi.org/10.1145/3312614.3312655openalex-snapshot
Cycle-Accurate NoC-based Convolutional Neural Network Simulator
inferredcites →https://doi.org/10.1145/3313231.3352377openalex-snapshot
Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks
inferredcites →https://doi.org/10.1145/3337770openalex-snapshot
Toward On-chip Network Security Using Runtime Isolation Mapping
inferredcites →https://doi.org/10.1145/344588.344618openalex-snapshot
Static scheduling algorithms for allocating directed task graphs to multiprocessors
inferredcites →https://doi.org/10.1201/9781315216072openalex-snapshot
Network-on-Chip: The Next Generation of System-on-Chip Integration
inferredcites →https://doi.org/10.1561/1000000011openalex-snapshot
The Chip Is the Network: Toward a Science of Network-on-Chip Design
inferredcites →https://doi.org/10.1587/elex.5.464openalex-snapshot
DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip
inferredcites →https://doi.org/10.1587/elex.6.1openalex-snapshot
Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip
inferredcites →https://doi.org/10.1587/elex.6.1737openalex-snapshot
Crinkle: A heuristic mapping algorithm for network on chip
inferredcites →https://doi.org/10.1587/elex.6.27openalex-snapshot
CGMAP: a new approach to Network-on-Chip mapping problem
inferredcites →https://doi.org/10.1587/elex.7.73openalex-snapshot
Elixir: A new bandwidth-constrained mapping for Networks-on-chip
inferredcites →https://doi.org/10.1587/transinf.2018edl8208openalex-snapshot
BMM: A Binary Metaheuristic Mapping Algorithm for Mesh-Based Network-on-Chip
inferredcites →https://doi.org/10.3390/electronics9010006openalex-snapshot
Improved Ant Colony Algorithm Based on Task Scale in Network on Chip (NoC) Mapping
inferredcites →https://doi.org/10.5555/1266366.1266390openalex-snapshot
An ILP formulation for system-level application mapping on network processor architectures
inferredcites →https://doi.org/10.5555/1266366.1266571openalex-snapshot
Congestion-controlled best-effort communication for networks-on-chip
inferredcites →https://doi.org/10.5555/2755753.2755808openalex-snapshot
A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms
inferredcites →https://doi.org/10.5555/3201607.3201637openalex-snapshot
Neu-NoC: a high-efficient interconnection network for accelerated neuromorphic systems
inferredcites →https://doi.org/10.5555/789083.1022804openalex-snapshot
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.7873/date.2013.083openalex-snapshot
SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model
inferredcites →https://doi.org/10.7873/date.2015.1127openalex-snapshot
A Cyber-Physical Systems Approach to Personalized Medicine: Challenges and Opportunities for NoC-based Multicore Platforms
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Pareto Technique Optimization for 3d Noc Architecture
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MANA:Multi-Application Mapping onto Mesh Network-on-Chip using ANN
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Travel Time-Based Task Mapping for NoC-Based DNN Accelerator
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Algorithmic Insights for Predicting Application Mapping & Its Analysis in Real Time Network on Chip Environments
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3D network-on-chip data acquisition system mapping based on reinforcement learning and improved attention mechanism
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HyDra: Hybrid Task Mapping Application Framework for NOC-Based MPSoCs
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A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based Platforms
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DA+BMAC: Distance-Aware Bidirectional Medium Access Control for Mesh Wireless Network-on-Chip
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Reinforcement Guided Genetic Algorithm for Application Mapping in Network-on-Chip Architectures: Toward Transparent and Efficient MPSoC Scheduling
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Optimization of Memory Oriented Network-on-Chip for FPGA
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Machine Learning Techniques for the Energy and Performance Improvement in Network-on-Chip (NoC)
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Long-Distance Communication via Pseudo-3D Networks-on-Chip
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Lightweight Monitoring Scheme for Flooding DoS Attack Detection in Multi-Tenant MPSoCs
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RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip
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Traffic Characterization Based Stochastic Modelling of Network-on-Chip
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The Learnable Model-Based Genetic Algorithm for the IP Mapping Problem
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Topology Exploration for Long-Distance Communication
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Policy Gradient-Based Core Placement Optimization for Multichip Many-Core Systems
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A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem
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Application Mapping Onto Manycore Processor Architectures Using Active Search Framework
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Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping
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A Novel Heuristic Neuron Grouping Algorithm for Deep Neural Network Accelerators
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Multicriteria Deming Regressive African Buffalo Optimized Mapping for 3D NoC Architecture Design
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Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: Memory systems, interconnects, and system integration
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Pareto technique optimization for 3D NOC architecture
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Test scheduling of network-on-chip using hybrid WOA-GWO algorithm
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Approaching the mapping limit with closed-loop mapping strategy for deploying neural networks on neuromorphic hardware
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IWO-IGA—A Hybrid Whale Optimization Algorithm Featuring Improved Genetic Characteristics for Mapping Real-Time Applications onto 2D Network on Chip
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An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture
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ET: A Metaheuristic Optimization Algorithm for Task Mapping in Network-on-Chip
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Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach
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Optimization Strategy of Regular NoC Mapping Using Genetic-Based Hyper-Heuristic Algorithm
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Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction
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Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip
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A Performance Constrained Metaheuristic Algorithm for 2D Mesh Based NoC
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