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Timing-Abstract Circuit Design in Transaction-Level Verilog

https://doi.org/10.1109/iccd.2017.91
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4020-8588-8_2openalex-snapshot
High-Level Synthesis: A Retrospective
inferredcites →https://doi.org/10.1007/978-1-4757-3281-8openalex-snapshot
System-on-Chip Methodologies & Design Languages
inferredcites →https://doi.org/10.1007/s10617-012-9096-8openalex-snapshot
An overview of today’s high-level synthesis tools
inferredcites →https://doi.org/10.1016/0167-6423(92)90005-vopenalex-snapshot
The Esterel synchronous programming language: design, semantics, implementation
inferredcites →https://doi.org/10.1049/ic.2010.0140openalex-snapshot
A theoretical and experimental review of SystemC front-ends
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1145/1363686.1364037openalex-snapshot
VHDL vs. Bluespec system verilog
inferredcites →https://doi.org/10.1145/2228360.2228584openalex-snapshot
Chisel
inferredcites →https://doi.org/10.1145/2543581.2543588openalex-snapshot
Synchronous digital circuits as functional programs
inferredcites →https://doi.org/10.1145/996566.996583openalex-snapshot
Modular scheduling of guarded atomic actions
inferredcites →https://doi.org/10.21236/ada243958openalex-snapshot
Optimal Retiming of Multi-Phase, Level-Clocked Circuits
inferredcites →https://doi.org/10.5860/choice.44-6278openalex-snapshot
Understanding Moore's law: four decades of innovation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-41131-2_10openalex-snapshot
Towards Formal Co-validation of Hardware and Software Timing Models of CPSs
inferred← citeshttps://doi.org/10.1109/dsa51864.2020.00073openalex-snapshot
Research and implementation of an automatic simulation tool
inferred← citeshttps://doi.org/10.1109/et59121.2023.10279744openalex-snapshot
A Practical Computer Architecture Education with RISC-V and TL-Verilog
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00075openalex-snapshot
Spade: An HDL Inspired by Modern Software Languages
inferred← citeshttps://doi.org/10.1109/iceccme55909.2022.9988191openalex-snapshot
Mixed Signal Simulation Marathon for Education and Employment
inferred← citeshttps://doi.org/10.1109/icsece58870.2023.10263395openalex-snapshot
Verification of CAN bus controller based on VIP
inferred← citeshttps://doi.org/10.1109/mcas.2021.3071608openalex-snapshot
FPGA Acceleration for Big Data Analytics: Challenges and Opportunities
inferred← citeshttps://doi.org/10.1145/3519939.3523455openalex-snapshot
PDL: a high-level hardware design language for pipelined processors
inferred← citeshttps://doi.org/10.1145/3532989openalex-snapshot
Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs
inferred← citeshttps://doi.org/10.1145/3656378openalex-snapshot
Modular Hardware Design of Pipelined Circuits with Hazards
inferred← citeshttps://doi.org/10.48550/arxiv.1811.01780openalex-snapshot
Top-Down Transaction-Level Design with TL-Verilog
inferred← citeshttps://doi.org/10.48550/arxiv.1811.12474openalex-snapshot
Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator
inferred← citeshttps://doi.org/10.55630/stem.2023.0513openalex-snapshot
A Model for Online Learning in Digital Hardware Design
inferred← citeshttps://doi.org/10.55630/stem.2024.0612openalex-snapshot
Visual Simulation of a Digital Hardware Model
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