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Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs

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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4020-8588-8_3openalex-snapshot
Catapult Synthesis: A Practical Introduction to Interactive C Synthesis
inferredcites →https://doi.org/10.1007/978-1-4020-8588-8_9openalex-snapshot
GAUT: A High-Level Synthesis Tool for DSP Applications
inferredcites →https://doi.org/10.1007/978-1-4419-6388-8openalex-snapshot
Power-efficient System Design
inferredcites →https://doi.org/10.1007/978-3-030-85665-6_38openalex-snapshot
Optimized Implementation of the HPCG Benchmark on Reconfigurable Hardware
inferredcites →https://doi.org/10.1007/978-3-319-16214-0_42openalex-snapshot
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL
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An overview of today’s high-level synthesis tools
inferredcites →https://doi.org/10.1007/s11390-020-9414-8openalex-snapshot
A Survey on Performance Optimization of High-Level Synthesis Tools
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Data path synthesis
inferredcites →https://doi.org/10.1016/j.sysarc.2019.08.001openalex-snapshot
A scala based framework for developing acceleration systems with FPGAs
inferredcites →https://doi.org/10.1038/nature14539openalex-snapshot
Deep learning
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The density advantage of configurable computing
inferredcites →https://doi.org/10.1109/92.820756openalex-snapshot
HML, a novel hardware description language and its translation to VHDL
inferredcites →https://doi.org/10.1109/asp-dac52403.2022.9712534openalex-snapshot
Large Forests and Where to “Partially” Fit Them
inferredcites →https://doi.org/10.1109/cgo.2004.1281665openalex-snapshot
LLVM: a compilation framework for lifelong program analysis & transformation
inferredcites →https://doi.org/10.1109/cgo.2019.8661197openalex-snapshot
Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code
inferredcites →https://doi.org/10.1109/codes-isss.2013.6659002openalex-snapshot
Improving polyhedral code generation for high-level synthesis
inferredcites →https://doi.org/10.1109/ectc.2012.6248841openalex-snapshot
Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer
inferredcites →https://doi.org/10.1109/fccm.2008.46openalex-snapshot
Kiwi: Synthesis of FPGA Circuits from Parallel Programs
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Designing Modular Hardware Accelerators in C with ROCCC 2.0
inferredcites →https://doi.org/10.1109/fccm.2016.46openalex-snapshot
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers
inferredcites →https://doi.org/10.1109/fccm.2018.00030openalex-snapshot
RapidWright: Enabling Custom Crafted Implementations for FPGAs
inferredcites →https://doi.org/10.1109/fccm.2019.00010openalex-snapshot
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs
inferredcites →https://doi.org/10.1109/fccm51124.2021.00023openalex-snapshot
The Importance of Being X-Drop: High Performance Genome Alignment on Reconfigurable Hardware
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Parallelizing applications into silicon
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DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler
inferredcites →https://doi.org/10.1109/fpl.2012.6339272openalex-snapshot
From opencl to high-performance hardware on FPGAS
inferredcites →https://doi.org/10.1109/fpl.2013.6645550openalex-snapshot
Bambu: A modular framework for the high level synthesis of memory-intensive applications
inferredcites →https://doi.org/10.1109/fpl.2014.6927454openalex-snapshot
Hardware system synthesis from Domain-Specific Languages
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The stanford pervasive parallelism lab
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Surviving the end of scaling of traditional micro processors in HPC
inferredcites →https://doi.org/10.1109/iccad.2017.8203780openalex-snapshot
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
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Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes
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Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93
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Timing-Abstract Circuit Design in Transaction-Level Verilog
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Generating Device-specific GPU Code for Local Operators in Medical Imaging
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Pearson Correlation Coefficient Acceleration for Modeling and Mapping of Neural Interconnections
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TiReX: Tiled Regular eXpression Matching Architecture
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A reconfigurable fabric for accelerating large-scale datacenter services
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Automatic Generation of Efficient Accelerators for Reconfigurable Hardware
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High-level synthesis of dataflow programs for signal processing systems
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Reconfigurable Computing Architectures
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SPIRAL: Extreme Performance Portability
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VLSI Array processors
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FPGA Architecture: Principles and Progression
inferredcites →https://doi.org/10.1109/mcsoc.2013.38openalex-snapshot
ArchHDL: A New Hardware Description Language for High-Speed Architectural Evaluation
inferredcites →https://doi.org/10.1109/mdt.2003.1214355openalex-snapshot
The evolution of systemverilog
inferredcites →https://doi.org/10.1109/mdt.2009.69openalex-snapshot
An Introduction to High-Level Synthesis
inferredcites →https://doi.org/10.1109/mdt.2009.83openalex-snapshot
High-Level Synthesis: Past, Present, and Future
inferredcites →https://doi.org/10.1109/mdt.2010.141openalex-snapshot
Customizable Domain-Specific Computing
inferredcites →https://doi.org/10.1109/micro.2014.50openalex-snapshot
PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research
inferredcites →https://doi.org/10.1109/micro.2018.00028openalex-snapshot
TAPAS: Generating Parallel Accelerators from Parallel Programs
inferredcites →https://doi.org/10.1109/mm.2011.68openalex-snapshot
Implementing Domain-Specific Languages for Heterogeneous Parallel Computing
inferredcites →https://doi.org/10.1109/mm.2020.2995854openalex-snapshot
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs
inferredcites →https://doi.org/10.1109/mm.2020.2996616openalex-snapshot
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
inferredcites →https://doi.org/10.1109/mm.2020.2998435openalex-snapshot
SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs
inferredcites →https://doi.org/10.1109/mm.2021.3088975openalex-snapshot
FPGA Computing
inferredcites →https://doi.org/10.1109/samos.2016.7818341openalex-snapshot
Design productivity of a high level synthesis compiler versus HDL
inferredcites →https://doi.org/10.1109/tcad.2006.884574openalex-snapshot
Measuring the Gap Between FPGAs and ASICs
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tcad.2015.2513673openalex-snapshot
A Survey and Evaluation of FPGA High-Level Synthesis Tools
inferredcites →https://doi.org/10.1109/tcad.2018.2834439openalex-snapshot
Are We There Yet? A Study on the State of High-Level Synthesis
inferredcites →https://doi.org/10.1109/tcad.2020.3012172openalex-snapshot
AnyHLS: High-Level Synthesis With Partial Evaluation
inferredcites →https://doi.org/10.1109/tetc.2022.3157948openalex-snapshot
An Energy-Efficient Domain-Specific Architecture for Regular Expressions
inferredcites →https://doi.org/10.1109/tpds.2015.2394802openalex-snapshot
HIPAcc: A Domain-Specific Language and Compiler for Image Processing
inferredcites →https://doi.org/10.1109/vlsi-dat.2017.7939656openalex-snapshot
High-level low-power system design optimization
inferredcites →https://doi.org/10.1109/wolfhpc.2014.11openalex-snapshot
ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers
inferredcites →https://doi.org/10.1145/161494.161501openalex-snapshot
Undecidability of static analysis
inferredcites →https://doi.org/10.1145/1749603.1749604openalex-snapshot
Compiling for reconfigurable computing
inferredcites →https://doi.org/10.1145/192724.192755openalex-snapshot
Characterizing the impact of predicated execution on branch prediction
inferredcites →https://doi.org/10.1145/1950413.1950423openalex-snapshot
LegUp
inferredcites →https://doi.org/10.1145/207110.207117openalex-snapshot
Accurate static branch prediction by value range propagation
inferredcites →https://doi.org/10.1145/2159542.2159547openalex-snapshot
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
inferredcites →https://doi.org/10.1145/2228360.2228472openalex-snapshot
Avoiding game over
inferredcites →https://doi.org/10.1145/2228360.2228584openalex-snapshot
Chisel
inferredcites →https://doi.org/10.1145/2491956.2462166openalex-snapshot
Terra
inferredcites →https://doi.org/10.1145/2499370.2462176openalex-snapshot
Halide
inferredcites →https://doi.org/10.1145/2584665openalex-snapshot
Delite
inferredcites →https://doi.org/10.1145/2601097.2601174openalex-snapshot
Darkroom
inferredcites →https://doi.org/10.1145/2656075.2656081openalex-snapshot
Code generation from a domain-specific language for C-based HLS of hardware accelerators
inferredcites →https://doi.org/10.1145/2656877.2656890openalex-snapshot
P4
inferredcites →https://doi.org/10.1145/2784731.2784754openalex-snapshot
Generating performance portable code using rewrite rules: from high-level functional expressions to high-performance OpenCL code
inferredcites →https://doi.org/10.1145/2786763.2694364openalex-snapshot
PolyMage
inferredcites →https://doi.org/10.1145/2814204.2814208openalex-snapshot
Shallow embedding of DSLs via online partial evaluation
inferredcites →https://doi.org/10.1145/2842615openalex-snapshot
On How to Accelerate Iterative Stencil Loops
inferredcites →https://doi.org/10.1145/2897824.2925892openalex-snapshot
Rigel
inferredcites →https://doi.org/10.1145/2954679.2872414openalex-snapshot
OpenPiton
inferredcites →https://doi.org/10.1145/2954679.2872415openalex-snapshot
Generating Configurable Hardware from Parallel Patterns
inferredcites →https://doi.org/10.1145/2967938.2967969openalex-snapshot
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs
inferredcites →https://doi.org/10.1145/3018743.3018758openalex-snapshot
Tapir
inferredcites →https://doi.org/10.1145/3020078.3021744openalex-snapshot
FINN
inferredcites →https://doi.org/10.1145/3050220.3050234openalex-snapshot
P4FPGA
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3079856.3080255openalex-snapshot
Stream-Dataflow Acceleration
inferredcites →https://doi.org/10.1145/3079856.3080256openalex-snapshot
Plasticine
inferredcites →https://doi.org/10.1145/3174243openalex-snapshot
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
inferredcites →https://doi.org/10.1145/3174243.3174250openalex-snapshot
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput
inferredcites →https://doi.org/10.1145/3174243.3174264openalex-snapshot
Dynamically Scheduled High-level Synthesis
inferredcites →https://doi.org/10.1145/3180481openalex-snapshot
RIPL
inferredcites →https://doi.org/10.1145/3186332openalex-snapshot
Toolflows for Mapping Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1145/3192366.3192379openalex-snapshot
Spatial: a language and compiler for application accelerators
inferredcites →https://doi.org/10.1145/3193827openalex-snapshot
FPGA Dynamic and Partial Reconfiguration
inferredcites →https://doi.org/10.1145/3195970.3196073openalex-snapshot
Mamba
inferredcites →https://doi.org/10.1145/3213846.3213848openalex-snapshot
Compiler fuzzing through deep learning
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The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/3240765.3240838openalex-snapshot
PolySA
inferredcites →https://doi.org/10.1145/3240765.3240850openalex-snapshot
SODA
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AnyDSL: a partial evaluation framework for programming high-performance libraries
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A new golden age for computer architecture
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Xilinx Adaptive Compute Acceleration Platform
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Network-on-Chip Programmable Platform in Versal TM ACAP Architecture
inferredcites →https://doi.org/10.1145/3289602.3293910openalex-snapshot
HeteroCL
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High-level synthesis of functional patterns with Lift
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Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing
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μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators
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A Survey of Coarse-Grained Reconfigurable Architecture and Design
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HeteroHalide
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Invited Tutorial
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Design and Preliminary Evaluation of OpenACC Compiler for FPGA with OpenCL and Stream Processing DSL
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Tools for Reduced Precision Computation
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The essence of Bluespec: a core language for rule-based hardware design
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SuSy
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A CAD-based methodology to optimize HLS code via the roofline model
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A Framework for Customizable FPGA-based Image Registration Accelerators
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AutoSA
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A compiler infrastructure for accelerator generators
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Warehouse-scale video acceleration: co-design and deployment in the wild
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Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components
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CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching
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Bidwidth analysis with application to silicon compilation
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Can programming be liberated from the von Neumann style?
inferredcites →https://doi.org/10.1145/381694.378860openalex-snapshot
SPL
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Reconfigurable computing
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On understanding types, data abstraction, and polymorphism
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design - ICCAD '02
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A quantitative analysis of the speedup factors of FPGAs over processors
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Advanced Systolic Design
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FPGA Architecture: Survey and Challenges
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Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project
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DFiant: A dataflow hardware description language
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A pythonic approach for rapid hardware prototyping and instrumentation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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PYXIS: A Highly Predictable Toolchain for FPGA Circuit Production of Advanced GNC Algorithm
inferred← citeshttps://doi.org/10.1109/tc.2026.3688303openalex-snapshot
DTRRS: A Dynamic Task Real-Time Reconfiguration and Scheduling Architecture for FPGAs in Embedded Systems
inferred← citeshttps://doi.org/10.1109/tpds.2022.3218898openalex-snapshot
Faber: A Hardware/SoftWare Toolchain for Image Registration
inferred← citeshttps://doi.org/10.1145/3607928openalex-snapshot
Hephaestus : Codesigning and Automating 3D Image Registration on Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1145/3613963openalex-snapshot
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?
inferred← citeshttps://doi.org/10.1145/3634920openalex-snapshot
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs
inferred← citeshttps://doi.org/10.1145/3635035.3637285openalex-snapshot
Flexible Systolic Array Platform on Virtual 2-D Multi-FPGA Plane
inferred← citeshttps://doi.org/10.1145/3717837openalex-snapshot
DFlows : A Flow-Based Programming Approach for a Polyglot Design-Space Exploration Framework
inferred← citeshttps://doi.org/10.1145/3723168openalex-snapshot
Rock the QASBA: Quantum Error Correction Acceleration via the Sparse Blossom Algorithm on FPGAs
inferred← citeshttps://doi.org/10.1145/3733239openalex-snapshot
QUEKUF : An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code
inferred← citeshttps://doi.org/10.1145/3764664openalex-snapshot
A Taxonomy of the High-Level Synthesis Ecosystem for Heterogeneous FPGA Systems
inferred← citeshttps://doi.org/10.1145/3786204openalex-snapshot
Composable Open Source Toolchain for Synthesizing Hardware Accelerators from OpenCL Command Buffers
inferred← citeshttps://doi.org/10.1145/3793550openalex-snapshot
Spade—A Modern Hardware Description Language
inferred← citeshttps://doi.org/10.1145/3805628openalex-snapshot
Are We Ready to Enable Satellite Autonomy Through on Board Image Registration?
inferred← citeshttps://doi.org/10.15379/ijmst.v10i3.2735openalex-snapshot
An In-Depth Analysis of Pythonic Paradigms for Rapid Hardware Prototyping and Instrumentation
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3511152/v1openalex-snapshot
FPGA-Based Image Denoising Using Adaptive Vector Directional Distance Filter: Performance Analysis and Comparison
inferred← citeshttps://doi.org/10.2139/ssrn.6216536openalex-snapshot
Direct Modification of FPGA Bitstream Under Physical Resource-Configuration Frame Mapping: From Model Construction to Functional Verification
inferred← citeshttps://doi.org/10.2139/ssrn.6642163openalex-snapshot
Direct Modification of FPGA Bitstream Under Physical Resource-Configuration Frame Mapping: From Model Construction to Functional Verification
inferred← citeshttps://doi.org/10.2478/bipie-2023-0011openalex-snapshot
A Methodology for the Synthesis and Evaluation of Hardware Accelerators
inferred← citeshttps://doi.org/10.3390/computers14050189openalex-snapshot
AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow
inferred← citeshttps://doi.org/10.3390/electronics12020425openalex-snapshot
SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching
inferred← citeshttps://doi.org/10.3390/electronics12244987openalex-snapshot
An Approach to the State Explosion Problem: SOPC Case Study
inferred← citeshttps://doi.org/10.3390/fi17110530openalex-snapshot
A Stateful Extension to P4THLS for Advanced Telemetry and Flow Control
inferred← citeshttps://doi.org/10.4204/eptcs.420.4openalex-snapshot
Static Communication Analysis for Hardware Design
inferred← citeshttps://doi.org/10.70675/f66d4d56z7efaz4c3dz968dz4dcae7036781openalex-snapshot
Using HLS to raise the design abstraction level for faster exploration of different CPU Micro-architectures
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