On the public citation graph

LVCMOS based Green Data Flip Flop Design on FPGA

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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s11277-016-3898-0openalex-snapshot
Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network
inferredcites →https://doi.org/10.1109/csnt.2015.131openalex-snapshot
Energy Efficient Counter Design Using Voltage Scaling on FPGA
inferredcites →https://doi.org/10.1109/iciinfs.2013.6731996openalex-snapshot
LVDCI I/O standard based green image ALU design on ultra scale FPGA
inferredcites →https://doi.org/10.1109/iicpe.2014.7115800openalex-snapshot
LVCMOS based energy efficient solar charge sensor design on FPGA
inferredcites →https://doi.org/10.1109/indiacom.2014.6828123openalex-snapshot
I/O standard based power optimized processor register design on ultra scale FPGA
inferredcites →https://doi.org/10.1109/ngct.2015.7375161openalex-snapshot
Stub-series terminated logic based energy Efficient Devnagri Unicode Reader design on 40nm and 28nm FPGA
inferredcites →https://doi.org/10.14257/ijca.2015.8.8.05openalex-snapshot
HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA
inferredcites →https://doi.org/10.14257/ijunesst.2015.8.8.15openalex-snapshot
Capacitance Scaling Based Energy Efficient and Tera Hertz Design of Malayalam Unicode Reader on FPGA
inferredcites →https://doi.org/10.4028/www.scientific.net/amr.893.798openalex-snapshot
Simulation of Voltage Scaling Aware Mobile Battery Charge Controller Sensor on FPGA

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.2139/ssrn.3356220openalex-extracted
Low Power Implementation of a RISC Machine Using Clock Gating Technique
inferred← citeshttps://doi.org/10.1007/978-981-99-6034-7_3openalex-snapshot
Design of Energy Efficient IoMT Electrocardiogram (ECG) Machine on 28 nm FPGA
inferred← citeshttps://doi.org/10.1108/wje-05-2021-0281openalex-snapshot
Comparative performance analysis of AES encryption algorithm for various LVCMOS on different FPGAs
inferred← citeshttps://doi.org/10.1109/iciteics61368.2024.10624742openalex-snapshot
Advancing Sustainability in Communication Systems: Design and Analysis of Energy-Efficient Flip-Flop Circuits on FPGA Platforms
inferred← citeshttps://doi.org/10.1109/mpcon66082.2025.11256764openalex-snapshot
Agentic AI Implementation in Healthcare Insurance Industry: A Comprehensive Framework for Automated Claims Processing and Risk Assessment
inferred← citeshttps://doi.org/10.1155/2021/4655400openalex-snapshot
VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication
inferred← citeshttps://doi.org/10.2174/0122103279273418231212053836openalex-snapshot
Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs
inferred← citeshttps://doi.org/10.35940/ijitee.l1005.10812s19openalex-snapshot
Design of Energy Efficient Control Unit and Implementation on High Performance FPGA
inferred← citeshttps://doi.org/10.35940/ijitee.l1005.10812s219openalex-snapshot
Design of Energy Efficient Control Unit and Implementation on High Performance FPGA
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