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A Cost-Effective Main Memory Organization for Future Servers

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/s1383-7621(98)00006-xopenalex-snapshot
Performance evaluation of computer architectures with main memory data compression
inferredcites →https://doi.org/10.1109/cmpcon.1993.289731openalex-snapshot
Memory servers for multicomputers
inferredcites →https://doi.org/10.1109/hpca.1999.744361openalex-snapshot
WildFire: a scalable path for SMPs
inferredcites →https://doi.org/10.1109/hpca.2001.903253openalex-snapshot
Performance of hardware compressed main memory
inferredcites →https://doi.org/10.1109/tvlsi.2003.812288openalex-snapshot
Gbit/s lossless data compression hardware
inferredcites →https://doi.org/10.1145/1055626.1055646openalex-snapshot
An in-depth look at computer performance growth
inferredcites →https://doi.org/10.1145/115952.115962openalex-snapshot
Evaluation of memory system extensions
inferredcites →https://doi.org/10.1145/242694.242709openalex-snapshot
The case for SRAM main memory
inferredcites →https://doi.org/10.1145/305138.305236openalex-snapshot
Efficient management of memory hierarchies in embedded DRAM systems
inferredcites →https://doi.org/10.1145/339647.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/342001.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/356989.356999openalex-snapshot
Power aware page allocation
inferredcites →https://doi.org/10.1145/378993.379007openalex-snapshot
Power aware page allocation
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1147/rd.461.0005openalex-snapshot
POWER4 system microarchitecture
inferredcites →https://doi.org/10.1147/sj.92.0078openalex-snapshot
Evaluation techniques for storage hierarchies

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/dasc-picom-datacom-cyberscitec.2016.161openalex-snapshot
Design and Implementation of Hybrid Shingled Recording RAID System
inferred← citeshttps://doi.org/10.1109/hpca.2018.00022openalex-snapshot
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
inferred← citeshttps://doi.org/10.1109/i2ct51068.2021.9417908openalex-snapshot
HeronEye: Survey on Coordinated and Efficient Huge Page Management to Fine-grained OS Support
inferred← citeshttps://doi.org/10.1109/iccd.2008.4751873openalex-snapshot
Prototyping a hybrid main memory using a virtual machine monitor
inferred← citeshttps://doi.org/10.1109/icpp.2014.18openalex-snapshot
Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory
inferred← citeshttps://doi.org/10.1109/ipdps.2012.71openalex-snapshot
Switching Optically-Connected Memories in a Large-Scale System
inferred← citeshttps://doi.org/10.1109/micro.2008.4771780openalex-snapshot
Implementing high availability memory with a duplication cache
inferred← citeshttps://doi.org/10.1109/micro.2014.56openalex-snapshot
Transparent Hardware Management of Stacked DRAM as Part of Memory
inferred← citeshttps://doi.org/10.1109/mm.2009.14openalex-snapshot
Server Designs for Warehouse-Computing Environments
inferred← citeshttps://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferred← citeshttps://doi.org/10.1109/tc.2012.119openalex-snapshot
Tiered Memory: An Iso-Power Memory Architecture to Address the Memory Power Wall
inferred← citeshttps://doi.org/10.1109/tvlsi.2010.2051569openalex-snapshot
Design and Characterization of a Multilevel DRAM
inferred← citeshttps://doi.org/10.1145/1176760.1176774openalex-snapshot
FlashCache
inferred← citeshttps://doi.org/10.1145/1394608.1382148openalex-snapshot
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
inferred← citeshttps://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferred← citeshttps://doi.org/10.1145/1555754.1555789openalex-snapshot
Disaggregated memory for expansion and sharing in blade servers
inferred← citeshttps://doi.org/10.1145/1555815.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferred← citeshttps://doi.org/10.1145/1555815.1555789openalex-snapshot
Disaggregated memory for expansion and sharing in blade servers
inferred← citeshttps://doi.org/10.1145/3037697.3037706openalex-snapshot
Thermostat
inferred← citeshttps://doi.org/10.1145/3093315.3037706openalex-snapshot
Thermostat
inferred← citeshttps://doi.org/10.1145/3093336.3037706openalex-snapshot
Thermostat
inferred← citeshttps://doi.org/10.1145/3093337.3037706openalex-snapshot
Thermostat
inferred← citeshttps://doi.org/10.1145/3132402.3132412openalex-snapshot
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