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Transparent Hardware Management of Stacked DRAM as Part of Memory

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/0167-739x(95)00024-mopenalex-snapshot
An argument for simple COMA
inferredcites →https://doi.org/10.1109/2.156381openalex-snapshot
DDM-a cache-only memory architecture
inferredcites →https://doi.org/10.1109/cmpcon.1993.289682openalex-snapshot
The KSR 1: bridging the gap between shared memory and MPPs
inferredcites →https://doi.org/10.1109/hicss.1994.323136openalex-snapshot
Simple COMA node implementations
inferredcites →https://doi.org/10.1109/hpca.1995.386535openalex-snapshot
An argument for simple COMA
inferredcites →https://doi.org/10.1109/hpca.1999.744361openalex-snapshot
WildFire: a scalable path for SMPs
inferredcites →https://doi.org/10.1109/hpca.2010.5416642openalex-snapshot
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
inferredcites →https://doi.org/10.1109/hpca.2013.6522354openalex-snapshot
Tiered-latency DRAM: A low latency and low cost DRAM architecture
inferredcites →https://doi.org/10.1109/ipdps.2005.12openalex-snapshot
A Cost-Effective Main Memory Organization for Future Servers
inferredcites →https://doi.org/10.1109/isca.2012.6237028openalex-snapshot
FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion
inferredcites →https://doi.org/10.1109/isscc.2014.6757361openalex-snapshot
5.9 Haswell: A family of IA 22nm processors
inferredcites →https://doi.org/10.1109/micro.2012.30openalex-snapshot
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
inferredcites →https://doi.org/10.1109/micro.2012.31openalex-snapshot
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
inferredcites →https://doi.org/10.1109/mm.2008.44openalex-snapshot
System-Level Performance Metrics for Multiprogram Workloads
inferredcites →https://doi.org/10.1109/mm.2010.38openalex-snapshot
Power7: IBM's Next-Generation Server Processor
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1109/tc.2001.970573openalex-snapshot
LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2366231.2337196openalex-snapshot
FLEXclusion
inferredcites →https://doi.org/10.1145/242694.242709openalex-snapshot
The case for SRAM main memory
inferredcites →https://doi.org/10.1145/2485922.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/2485922.2485958openalex-snapshot
Resilient die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2503210.2503215openalex-snapshot
Exploring DRAM organizations for energy-efficient and resilient exascale memories
inferredcites →https://doi.org/10.1145/2628071.2628089openalex-snapshot
ATCache
inferredcites →https://doi.org/10.1145/264107.264205openalex-snapshot
Reactive NUMA
inferredcites →https://doi.org/10.1145/264107.264206openalex-snapshot
The SGI Origin
inferredcites →https://doi.org/10.1145/291006.291032openalex-snapshot
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
inferredcites →https://doi.org/10.1145/291069.291032openalex-snapshot
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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HBM-Resident Prefetching for Heterogeneous Memory System
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PRO: A periodical reset optimized page migration scheme for hybrid memory system
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Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
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SwapX: An NVM-Based Hierarchical Swapping Framework
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WIRD: An Efficiency Migration Scheme in Hybrid DRAM and PCM Main Memory for Image Processing Applications
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ProactivePIM: Accelerating Weight-Sharing Embedding Layer With PIM for Scalable Recommendation System
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A Metadata Prefetching Mechanism for Hybrid Memory Architectures
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Bumblebee: A MemCache Design for Die-stacked and Off-chip Heterogeneous Memory Systems
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Efficient footprint caching for Tagless DRAM Caches
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SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization
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MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories
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Design and Analysis of an APU for Exascale Computing
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GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
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ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
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Reliability-Aware Data Placement for Heterogeneous Memory Architecture
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PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems
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Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
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Stealth-Persist: Architectural Support for Persistent Applications in Hybrid Memory Systems
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Baryon: Efficient Hybrid Memory Management with Compression and Sub-Blocking
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Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory
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Dynamic prefetcher reconfiguration for diverse memory architectures
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Puzzle Memory: Multifractional Partitioned Heterogeneous Memory Scheme
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TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems
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Supporting Dynamic Translation Granularity for Hybrid Memory Systems
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Bandwidth-aware DRAM page migration for heterogeneous mobile memory systems
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LLC-Guided Data Migration in Hybrid Memory Systems
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The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
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SELF: A High Performance and Bandwidth Efficient Approach to Exploiting Die-Stacked DRAM as Part of Memory
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Performance Potential of Mixed Data Management Modes for Heterogeneous Memory Systems
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Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities
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Blenda: Dynamically-Reconfigurable Stacked DRAM
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NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
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Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems
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Hardware Memory Management for Future Mobile Hybrid Memory Systems
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Near Data Processing
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memif
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