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Improving Energy-Efficiency by Bypassing Trivial Computations

https://doi.org/10.1109/ipdps.2005.253

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/12.48865openalex-snapshot

Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers

inferredcites →https://doi.org/10.1109/iccd.2002.1106814openalex-snapshot

Improving processor performance by simplifying and bypassing trivial computations

inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot

Wattch: a framework for architectural-level power analysis and optimizations

inferredcites →https://doi.org/10.1109/ispass.2004.1291358openalex-snapshot

Dynamically reducing pressure on the physical register file through simple register sharing

inferredcites →https://doi.org/10.1109/micro.1996.566464openalex-snapshot

Exceeding the dataflow limit via value prediction

inferredcites →https://doi.org/10.1109/tcad.2002.801096openalex-snapshot

Value-sensitive automatic code specialization for embedded software

inferredcites →https://doi.org/10.1145/264107.264200openalex-snapshot

Dynamic instruction reuse

inferredcites →https://doi.org/10.1145/339647.339657openalex-snapshot

Wattch

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.micpro.2007.06.003openalex-snapshot

Partial resolution for redundant operation table

inferred← citeshttps://doi.org/10.1016/j.micpro.2007.10.001openalex-snapshot

Early detection and bypassing of trivial operations to improve energy efficiency of processors

inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218547openalex-snapshot

Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs

inferred← citeshttps://doi.org/10.1109/icsamos.2006.300805openalex-snapshot

Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations

inferred← citeshttps://doi.org/10.1109/isca52012.2021.00035openalex-snapshot

Opening Pandora’s Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data

inferred← citeshttps://doi.org/10.1109/isca66397.2026.00045openalex-snapshot

Helium: Quantifying Microarchitectural Side-Channel Leakage with Probabilistic Guarantees

inferred← citeshttps://doi.org/10.1109/micro.2007.41openalex-snapshot

Composable Lightweight Processors

inferred← citeshttps://doi.org/10.1109/micro.2007.9openalex-snapshot

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

inferred← citeshttps://doi.org/10.1109/sies.2007.4297321openalex-snapshot

Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications

inferred← citeshttps://doi.org/10.1145/3581784.3607052openalex-snapshot

TrivialSpy: Identifying Software Triviality via Fine-grained and Dataflow-based Value Profiling

inferred← citeshttps://doi.org/10.1145/3620665.3640400openalex-snapshot

Avoiding Instruction-Centric Microarchitectural Timing Channels Via Binary-Code Transformations

inferred← citeshttps://doi.org/10.1145/3658644.3670319openalex-snapshot

Testing Side-channel Security of Cryptographic Implementations against Future Microarchitectures

inferred← citeshttps://doi.org/10.14722/ndss.2022.24215openalex-snapshot

SynthCT: Towards Portable Constant-Time Code

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