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Composable Lightweight Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Plausible Motion Simulation for Computer Graphics Animation
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Resource allocation problems: Algorithmic approaches
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Performance and accuracy of hardware-oriented native-, emulated- and mixed-precision solvers in FEM simulations
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A chip-multiprocessor architecture with speculative multithreading
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Baring it all to software: Raw machines
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Exploiting trivial and redundant computation
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Power Efficient Processor Architecture and The Cell Processor
inferredcites →https://doi.org/10.1109/hpca.2007.346182openalex-snapshot
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
inferredcites →https://doi.org/10.1109/iccd.2002.1106814openalex-snapshot
Improving processor performance by simplifying and bypassing trivial computations
inferredcites →https://doi.org/10.1109/iccd.2006.4380806openalex-snapshot
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
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On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions
inferredcites →https://doi.org/10.1109/ipdps.2005.253openalex-snapshot
Improving Energy-Efficiency by Bypassing Trivial Computations
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/isca.2001.937451openalex-snapshot
Power and energy reduction via pipeline balancing
inferredcites →https://doi.org/10.1109/isca.2001.937452openalex-snapshot
Energy-effective issue logic
inferredcites →https://doi.org/10.1109/isca.2004.1310764openalex-snapshot
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
inferredcites →https://doi.org/10.1109/jssc.2006.870924openalex-snapshot
A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a CELL Processor
inferredcites →https://doi.org/10.1109/mc.2003.1250883openalex-snapshot
Dynamically tuning processor resources with adaptive processing
inferredcites →https://doi.org/10.1109/mc.2004.65openalex-snapshot
Scaling to the end of silicon with EDGE architectures
inferredcites →https://doi.org/10.1109/micro.1999.809463openalex-snapshot
Selective cache ways: on-demand cache resource allocation
inferredcites →https://doi.org/10.1109/micro.2001.991108openalex-snapshot
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
inferredcites →https://doi.org/10.1109/micro.2003.1253185openalex-snapshot
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
inferredcites →https://doi.org/10.1109/micro.2004.12openalex-snapshot
Conjoined-Core Chip Multiprocessing
inferredcites →https://doi.org/10.1109/micro.2005.13openalex-snapshot
Automatic Thread Extraction with Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/micro.2006.19openalex-snapshot
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/pact.2001.953283openalex-snapshot
Basic block distribution analysis to find periodic behavior and simulation points in applications
inferredcites →https://doi.org/10.1109/sc.2000.10029openalex-snapshot
A Scalable Cross-Platform Infrastructure for Application Performance Tuning Using Hardware Counters
inferredcites →https://doi.org/10.1109/tc.2005.119openalex-snapshot
Fuzzy Memoization for Floating-Point Multimedia Applications
inferredcites →https://doi.org/10.1145/1006209.1006254openalex-snapshot
Back-end assignment schemes for clustered multithreaded processors
inferredcites →https://doi.org/10.1145/1176760.1176802openalex-snapshot
Improving the performance and power efficiency of shared helpers in CMPs
inferredcites →https://doi.org/10.1145/1183316.1183326openalex-snapshot
Enabling real-time physics simulation in future interactive entertainment
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Physical simulation for animation and visual effects
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Anatomy of high-performance matrix multiplication
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The case for a single-chip multiprocessor
inferredcites →https://doi.org/10.1145/237090.237173openalex-snapshot
Value locality and load value prediction
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/782814.782820openalex-snapshot
Partitioned first-level cache design for clustered microarchitectures
inferredcites →https://doi.org/10.1145/859618.859667openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
inferredcites →https://doi.org/10.1155/s1110865702205090openalex-snapshot
Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Composable Multicore Chips
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Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA
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Approximate Computing and Its Application to Hardware Security
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Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
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Dynamic Resource Tuning for Flexible Core Chip Multiprocessors
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Technical Difficulties and Development Trend
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Advancing synthesis of decision tree-based multiple classifier systems: an approximate computing case study
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Program-based dynamic precision selection framework with a dual-mode unified shader for mobile GPUs
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Global register alias table: Boosting sequential program on multi-core
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ReKonf: Dynamically reconfigurable multiCore architecture
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The Principle and Progress of Dynamically Reconfigurable Computing Technologies
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
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Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning
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Global Register Alias Table: Executing Sequential Program on Multi-Core
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On-Chip Operating System Design for NoC-Based CMP
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Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology
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Enabling dynamic heterogeneity through core-on-core stacking
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Formulating MITF for a Multicore Processor with SEU Tolerance
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StreaMorph: A case for synthesizing energy-efficient adaptive programs using high-level abstractions
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Edge-Supported Approximate Analysis for Long Running Computations
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Green Data Mining using Approximate Computing: An experimental analysis with Rule Mining
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FlexCore: A Reconfigurable Processor Supporting Flexible, Dynamic Morphing
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Fundamental performance constraints in horizontal fusion of in-order cores
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LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores
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Exploiting criticality to reduce bottlenecks in distributed uniprocessors
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Dynamically heterogeneous cores through 3D resource pooling
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Illusionist: Transforming lightweight cores into aggressive cores on demand
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How to implement effective prediction and forwarding for fusable dynamic multicore architectures
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BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing
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Enhancing Server Efficiency in the Face of Killer Microseconds
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Localizing Loads Execution in a Data Cache Distributed Processor Architecture
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A study on performance benefits of core morphing in an asymmetric multicore processor
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A co-processor approach for accelerating data-structure intensive algorithms
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On dynamic polymorphing of a superscalar core for improving energy efficiency
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Dynamic front-end sharing in graphics processing units
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The heterogeneous block architecture
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Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core
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Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures
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DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs
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Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis
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Distributed Control Independence for Composable Multi-processors
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Thread-Sensitive Modulo Scheduling for Multicore Processors
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Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture
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Scheduling multithreaded applications onto heterogeneous composite cores architecture
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Exploiting approximate value locality for data synchronization on multi-core processors
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The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors
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Using Multiple Threads to Accelerate Single Thread Performance
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Very Large-Scale Integrated Processor
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A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware
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Harmony: Collection and analysis of parallel block vectors
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Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading
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Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network
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A Neural Network-Based Approach to Dynamic Core Morphing for AMPs
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AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores
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Evaluating asymmetric multiprocessing for mobile applications
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A study on polymorphing superscalar processor dynamically to improve power efficiency
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Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores
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Design and Implementation of an Efficient and Realistic Cooperative Core Architecture
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Scalable Dynamic Task Scheduling on Adaptive Many-Core
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Modeling and simulation of distributed fetch front-end based on M5-edge
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Strategies for mapping dataflow blocks to distributed hardware
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Erasing Core Boundaries for Robust and Configurable Performance
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MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP
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Composite Cores: Pushing Heterogeneity Into a Core
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big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
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Toward Dynamic Precision Scaling
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Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures
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Core-Selectability in Chip Multiprocessors
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Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores
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FACRA: Flexible-Core Architecture Chip Resource Abstractor
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Approximating a Multi-Grid Solver
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ReCompAc: Reconfigurable compute accelerator
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Dynamic-vector execution on a general purpose EDGE chip multiprocessor
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Imposing coarse-grained reconfiguration to general purpose processors
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Customized architectures for faster route finding in GPS-based navigation systems
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Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
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Dynamic Tolerance Region Computing for Multimedia
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Task Scheduling on Adaptive Multi-Core
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Scaling Power and Performance viaProcessor Composability
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Exploring Fine-Grained Heterogeneity with Composite Cores
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NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications
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XMeter: Finding Approximable Functions and Predicting Their Accuracy
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Learning-Based Quality Management for Approximate Communication in Network-on-Chips
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LEXACT: Low Energy N-Modular Redundancy Using Approximate Computing for Real-Time Multicore Processors
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Hybrid Dataflow/von-Neumann Architectures
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Exploring Heterogeneity within a Core for Improved Power Efficiency
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An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures
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Quantitative Analysis of Inter-block Dependence in Speculative Execution
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ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling
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iMODE (interactive MOod Detection Engine) Processor
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Implementation of core coalition on FPGAs
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Counting Dependence Predictors
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Enabling Dynamic Heterogeneity Through Core-on-Core Stacking
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A Survey of Techniques for Approximate Computing
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Input responsiveness: using canary inputs to dynamically steer approximation
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Input responsiveness: using canary inputs to dynamically steer approximation
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Efficiently scaling out-of-order cores for simultaneous multithreading
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A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor
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High-Level Synthesis of Approximate Designs under Real-Time Constraints
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DiAG: a dataflow-inspired architecture for general-purpose processors
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Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane
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PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures
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SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads
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Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units
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Approximate Computing for Robotic path planning -- Experimentation, Case Study and Practical Implications
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Reconfigurable computing: toward software defined chips
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Very Large-Scale Integrated Processor
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Behavioral design of approximate arithmetic systems for reliable computing
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The Advantages and Challenges of Spatial Computation
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Power-Efficient Computer Architectures: Recent Advances
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A language extension set to generate adaptive versions automatically
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
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On Dynamic Precision Scaling
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Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
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Integrated Programmable-Array accelerator to design heterogeneous ultra-low power manycore architectures
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Energy Efficient Multi-Core Processing
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