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Packet Routing in Dynamically Changing Networks on Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-24714-2_11openalex-snapshot
A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware
inferredcites →https://doi.org/10.1007/978-3-540-30117-2_121openalex-snapshot
A Dynamic NoC Approach for Communication in Reconfigurable Devices
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_58openalex-snapshot
Networks on Chip as Hardware Components of an OS for Reconfigurable Systems
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/54.825678openalex-snapshot
Fast template placement for reconfigurable computing systems
inferredcites →https://doi.org/10.1109/ipdps.2003.1213329openalex-snapshot
Fast online task placement on FPGAs: free space partitioning and 2D-hashing
inferredcites →https://doi.org/10.1109/mcas.2004.1330747openalex-snapshot
Feature - Xpipes : a network-on-chip architecture for gigascale systems-on-chip
inferredcites →https://doi.org/10.1109/real.2003.1253269openalex-snapshot
Online scheduling and placement of real-time tasks to partially reconfigurable devices
inferredcites →https://doi.org/10.1109/tpds.2004.1264810openalex-snapshot
Exploiting global knowledge to achieve self-tuned congestion control for k-ary n-cube networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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An Analyzable On-Chip Network Architecture for Embedded Systems
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ReCoNodes—Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices
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IoT traffic management using deep learning based on osmotic cloud to edge computing
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Adaptive job routing and scheduling
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CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
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A Novel Optical Mesh Network-on-Chip for Gigascale Systems-on-Chip
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Droplet Routing in the Synthesis of Digital Microfluidic Biochips
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Minimizing Communication Cost for Reconfigurable Slot Modules
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CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs
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Hybrid Fault Detection for Adaptive NoC
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A brief overview of the challenges of the multicore roadmap
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Optimized Q-learning model for distributing traffic in on-Chip Networks
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NoC-Based FPGA: Architecture and Routing
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Fault-tolerant architecture and deflection routing for degradable NoC switches
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HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks
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Application of Deep Compression Technique in Spiking Neural Network Chip
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Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
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End-to-end error correction and online diagnosis for on-chip networks
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Smart Reliable Network-on-Chip
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A Survey on Deep Learning for the Routing Layer of Computer Network
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Performance analysis of congestion-aware Q-routing algorithm for network on chip
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Performance improvement of application-specific network on chip using machine learning algorithms
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Secure Network-on-Chip Against Black Hole and Tampering Attacks
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Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.
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Efficient Design of Error Recovery and Improve the Performance Using Mesh of Ring Topology Based NoC
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Efficient techniques for testing networks on chips. (c2010)
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A Survey of Machine Learning Applied to Computer Architecture Design
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A Machine Learning Approach to Routing
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Auto-tuning Distributed Stream Processing Systems using Reinforcement Learning
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Lossless static vs. dynamic reconfiguration of interconnection networks in parallel and distributed computer systems
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Etude et conception d'un réseau sur puce dynamiquement adaptable pour la vision embarquée
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