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Methods for fault tolerance in networks-on-chip

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Outgoing claims: the papers this work cites, builds on, or argues with.

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Fault-Tolerant Design

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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

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Bibliographical review on reconfigurable fault-tolerant control systems

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Electron transport through broken down ultra-thin SiO2 layers in MOS devices

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Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

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Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin oxides

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Fundamentals of Error-Correcting Codes

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Low-power and error protection coding for network-on-chip traffic

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Designing fault-tolerant network-on-chip router architecture

inferredcites →https://doi.org/10.1080/07408170304426openalex-snapshot

Reliability of Computer Systems and Networks Fault Tolerance, Analysis, and Design

inferredcites →https://doi.org/10.1109/12.392844openalex-snapshot

Fault-tolerant wormhole routing algorithms for mesh networks

inferredcites →https://doi.org/10.1109/12.841127openalex-snapshot

Threshold-based mechanisms to discriminate transient from intermittent faults

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Autonet: a high-speed, self-configuring local area network using point-to-point links

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Modeling the wiring of deep submicron ICs

inferredcites →https://doi.org/10.1109/71.926168openalex-snapshot

A fault-tolerant routing scheme for meshes with nonconvex faults

inferredcites →https://doi.org/10.1109/92.863617openalex-snapshot

Toward achieving energy efficiency in presence of deep submicron noise

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Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003

inferredcites →https://doi.org/10.1109/asap.2007.4429960openalex-snapshot

Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router

inferredcites →https://doi.org/10.1109/date.2003.1253703openalex-snapshot

On-chip stochastic communication [SoC applications]

inferredcites →https://doi.org/10.1109/date.2006.244033openalex-snapshot

Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness

inferredcites →https://doi.org/10.1109/date.2007.364538openalex-snapshot

Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks

inferredcites →https://doi.org/10.1109/date.2011.5763096openalex-snapshot

Architectures for online error detection and recovery in multicore processors

inferredcites →https://doi.org/10.1109/dft.2006.22openalex-snapshot

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding

inferredcites →https://doi.org/10.1109/dft.2006.46openalex-snapshot

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

inferredcites →https://doi.org/10.1109/dft.2007.14openalex-snapshot

Fault Tolerant Source Routing for Network-on-chip

inferredcites →https://doi.org/10.1109/dft.2007.20openalex-snapshot

Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code

inferredcites →https://doi.org/10.1109/dft.2007.55openalex-snapshot

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model

inferredcites →https://doi.org/10.1109/dft.2008.40openalex-snapshot

Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment

inferredcites →https://doi.org/10.1109/dft.2009.41openalex-snapshot

Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels

inferredcites →https://doi.org/10.1109/dsd.2011.54openalex-snapshot

Design of Fault Tolerant Network Interfaces for NoCs

inferredcites →https://doi.org/10.1109/dsn.2002.1028924openalex-snapshot

Modeling the effect of technology trends on the soft error rate of combinational logic

inferredcites →https://doi.org/10.1109/dsn.2005.4openalex-snapshot

Proceedings. 2005 International Conference on Dependable Systems and Networks

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Exploring Fault-Tolerant Network-on-Chip Architectures

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Living with Failure: Lessons from Nature?

inferredcites →https://doi.org/10.1109/ets.2007.41openalex-snapshot

Test Configurations for Diagnosing Faulty Links in NoC Switches

inferredcites →https://doi.org/10.1109/ets.2011.33openalex-snapshot

Structural Test for Graceful Degradation of NoC Switches

inferredcites →https://doi.org/10.1109/euc.2011.36openalex-snapshot

Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies

inferredcites →https://doi.org/10.1109/ewdts.2008.5580142openalex-snapshot

Reliable NoC architecture utilizing a robust rerouting algorithm

inferredcites →https://doi.org/10.1109/fpl.2005.1515715openalex-snapshot

Dynoc: a dynamic infrastructure for communication in dynamically reconfigurable devices

inferredcites →https://doi.org/10.1109/fpl.2009.5272274openalex-snapshot

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

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FPGA defect tolerance: impact of granularity.

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Fault-tolerant wormhole routing in meshes

inferredcites →https://doi.org/10.1109/hpca.2006.1598108openalex-snapshot

BulletProof: A Defect~Tolerant CMP Switch Architecture

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Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

inferredcites →https://doi.org/10.1109/iccad.1999.810665openalex-snapshot

Fault modeling and simulation for crosstalk in system-on-chip interconnects

inferredcites →https://doi.org/10.1109/iccd.1993.393415openalex-snapshot

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93

inferredcites →https://doi.org/10.1109/iccd.2010.5647663openalex-snapshot

A fine-grained link-level fault-tolerant mechanism for networks-on-chip

inferredcites →https://doi.org/10.1109/iccd.2010.5647684openalex-snapshot

Crosstalk modeling to predict channel delay in Network-on-Chips

inferredcites →https://doi.org/10.1109/iccet.2010.5485579openalex-snapshot

Fault-tolerant routing in A PRDT(2,1)-based NoC

inferredcites →https://doi.org/10.1109/icpp.1999openalex-snapshot

Proceedings of the 1999 International Conference on Parallel Processing

inferredcites →https://doi.org/10.1109/icpp.2002.1040880openalex-snapshot

Fault-tolerant and deadlock-free routing in 2-D meshes using rectilinear-monotone polygonal fault blocks

inferredcites →https://doi.org/10.1109/iedm.2003.1269336openalex-snapshot

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

inferredcites →https://doi.org/10.1109/iolts.2006.44openalex-snapshot

On-line Fault Detection and Location for NoC Interconnects

inferredcites →https://doi.org/10.1109/iolts.2007.24openalex-snapshot

Configurable Error Control Scheme for NoC Signal Integrity

inferredcites →https://doi.org/10.1109/ipdps.2000openalex-snapshot

Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000

inferredcites →https://doi.org/10.1109/ipdps.2005.323openalex-snapshot

Packet Routing in Dynamically Changing Networks on Chip

inferredcites →https://doi.org/10.1109/ipdps.2009.5161048openalex-snapshot

A new mechanism to deal with process variability in NoC links

inferredcites →https://doi.org/10.1109/isca.2006.6openalex-snapshot

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

inferredcites →https://doi.org/10.1109/iscas.2005.1464951openalex-snapshot

Power analysis of link level and end-to-end data protection in networks on chip

inferredcites →https://doi.org/10.1109/iscas.2010.5537694openalex-snapshot

Error control integration scheme for reliable NoC

inferredcites →https://doi.org/10.1109/ispa.2009.62openalex-snapshot

Fault-Tolerant Routing Schemes for Wormhole Mesh

inferredcites →https://doi.org/10.1109/isqed.2006.137openalex-snapshot

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

inferredcites →https://doi.org/10.1109/isqed.2008.4479836openalex-snapshot

Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation

inferredcites →https://doi.org/10.1109/isscc.1994openalex-snapshot

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94

inferredcites →https://doi.org/10.1109/isscc.2007.373606openalex-snapshot

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

inferredcites →https://doi.org/10.1109/isscc.2008.4523070openalex-snapshot

TILE64 - Processor: A 64-Core SoC with Mesh Interconnect

inferredcites →https://doi.org/10.1109/isscs.2009.5206183openalex-snapshot

Multi network interface architectures for fault tolerant Network-on-Chip

inferredcites →https://doi.org/10.1109/isvlsi.2004.1339507openalex-snapshot

Fault tolerant algorithms for network-on-chip interconnect

inferredcites →https://doi.org/10.1109/isvlsi.2007.21openalex-snapshot

Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding

inferredcites →https://doi.org/10.1109/mdt.2004.8openalex-snapshot

Defect and error tolerance in the presence of massive numbers of defects

inferredcites →https://doi.org/10.1109/mdt.2005.104openalex-snapshot

Analysis of error recovery schemes for networks on chips

inferredcites →https://doi.org/10.1109/mdt.2005.69openalex-snapshot

Soft Errors in Advanced Computer Systems

inferredcites →https://doi.org/10.1109/mdt.2007.128openalex-snapshot

Crosstalk- and SEU-Aware Networks on Chips

inferredcites →https://doi.org/10.1109/mdt.2010.50openalex-snapshot

Modeling Process Variability in Scaled CMOS Technology

inferredcites →https://doi.org/10.1109/micro.1996openalex-snapshot

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29

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Efficient unicast and multicast support for CMPs

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Trends and challenges in VLSI circuit reliability

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Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation

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A 5-GHz Mesh Interconnect for a Teraflops Processor

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Research Challenges for On-Chip Interconnection Networks

inferredcites →https://doi.org/10.1109/mspec.2011.5753241openalex-snapshot

An odomoeter for CPUs

inferredcites →https://doi.org/10.1109/nocs.2007.39openalex-snapshot

Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips

inferredcites →https://doi.org/10.1109/nocs.2007.44openalex-snapshot

Towards Open Network-on-Chip Benchmarks

inferredcites →https://doi.org/10.1109/nocs.2008.4492721openalex-snapshot

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

inferredcites →https://doi.org/10.1109/nocs.2009.5071441openalex-snapshot

Fault-tolerant architecture and deflection routing for degradable NoC switches

inferredcites →https://doi.org/10.1109/nocs.2009.5071442openalex-snapshot

Adaptive stochastic routing in fault-tolerant on-chip networks

inferredcites →https://doi.org/10.1109/nocs.2010.12openalex-snapshot

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

inferredcites →https://doi.org/10.1109/nocs.2010.24openalex-snapshot

Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip

inferredcites →https://doi.org/10.1109/nocs.2012.27openalex-snapshot

Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip

inferredcites →https://doi.org/10.1109/norchp.2005.1596991openalex-snapshot

A dynamic routing mechanism for network on chip

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ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

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The viterbi algorithm

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LTR: A low-overhead and reliable routing algorithm for network on chips

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A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS)

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A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

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Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology

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Error control schemes for on-chip communication links: the energy-reliability tradeoff

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Soft-Error-Rate-Analysis (SERA) Methodology

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Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

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Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip

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Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

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Convolutional Codes and Their Performance in Communication Systems

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On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects

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A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links

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Basic concepts and taxonomy of dependable and secure computing

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Proceedings International Test Conference 2003

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Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk

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Combinational Logic Soft Error Correction

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End-to-end error correction and online diagnosis for on-chip networks

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Basic mechanisms and modeling of single-event upset in digital microelectronics

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Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes

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A theory for deadlock-free dynamic network reconfiguration. Part I

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A methodology for developing deadlock-free dynamic network reconfiguration processes. Part II

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A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms

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Coding for system-on-chip networks: a unified framework

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Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects

inferredcites →https://doi.org/10.1109/tvlsi.2009.2013711openalex-snapshot

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

inferredcites →https://doi.org/10.1109/tvlsi.2011.2156436openalex-snapshot

Dual-Layer Adaptive Error Control for Network-on-Chip Links

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Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems

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Time redundancy based soft-error tolerance to rescue nanometer technologies

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Circuit Failure Prediction and Its Application to Transistor Aging

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Key research problems in NoC design

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Design and analysis of an NoC architecture from performance, reliability and energy perspective

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Performance driven reliable link design for networks on chips

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A survey of research and practices of Network-on-chip

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Reliability challenges for 45nm and beyond

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A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip

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A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

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Evaluation of SEU and crosstalk effects in network-on-chip switches

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On-chip communication architecture exploration

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Thousand core chips

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An on-chip NBTI sensor for measuring PMOS threshold voltage degradation

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A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

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Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router

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Vicis

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A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip

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Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration

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A distributed and topology-agnostic approach for on-line NoC testing

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Enabling system-level modeling of variation-induced faults in networks-on-chips

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Formally enhanced runtime verification to ensure NoC functional correctness

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Cost reduction and evaluation of temporary faults detecting technique

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A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip

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DyAD

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Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

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Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip

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Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip

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~ " " " ' l I ~ " " -" . : -· " J

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A highly resilient routing algorithm for fault-tolerant NoCs

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Fault modeling and simulation for crosstalk in system-on-chip interconnects

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On-Chip Stochastic Communication

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Razor: a low-power pipeline based on circuit-level timing speculation

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Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A new architecture for online error detection and isolation in network on chip

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RescueSNN: enabling reliable executions on spiking neural network accelerators under permanent faults

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Efficient Communication Protection of Many-Core Systems against Active Attackers

inferred← citeshttps://doi.org/10.3390/electronics9020342openalex-snapshot

NoCGuard: A Reliable Network-on-Chip Router Architecture

inferred← citeshttps://doi.org/10.3390/jlpea11010007openalex-snapshot

Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper

inferred← citeshttps://doi.org/10.3390/jlpea9010011openalex-snapshot

Tolerating Permanent Faults in the Input Port of the Network on Chip Router

inferred← citeshttps://doi.org/10.3390/s19245416openalex-snapshot

Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design

inferred← citeshttps://doi.org/10.3850/9783981537079_0158openalex-snapshot

Providing Formal Latency Guarantees for ARQ-based Protocols in Networks-on-Chip

inferred← citeshttps://doi.org/10.3850/9783981537079_0400openalex-snapshot

Correct Runtime Operation for NoCs through Adaptive-Region Protection

inferred← citeshttps://doi.org/10.3850/9783981537079_0513openalex-snapshot

Fault-Tolerant 3-D Network-on-Chip Design using Dynamic Link Sharing

inferred← citeshttps://doi.org/10.3990/1.9789036537728openalex-snapshot

Towards a dependable homegeneous many-processor system-on-chip

inferred← citeshttps://doi.org/10.4018/978-1-4666-6034-2.ch001openalex-snapshot

Self-Adaptive SoCs for Dependability

inferred← citeshttps://doi.org/10.4018/ijertcs.2019070105openalex-snapshot

A New Fault Tolerant Routing Algorithm for Networks on Chip

inferred← citeshttps://doi.org/10.48550/arxiv.1908.00289openalex-snapshot

Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip

inferred← citeshttps://doi.org/10.48550/arxiv.2006.11025openalex-snapshot

Design of a Near-Ideal Fault-Tolerant Routing Algorithm for Network-on-Chip-Based Multicores

inferred← citeshttps://doi.org/10.5120/ijca2016909552openalex-snapshot

NoCGIN: A Gamma Interconnection Network as NoC Interconnect

inferred← citeshttps://doi.org/10.70675/f4260003z4c14z4ff4z90c3zf7e12f9cded4openalex-snapshot

Etude de la fiabilité des algorithmes self-convergeants face aux soft-erreurs

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