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An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-58429-3_32openalex-snapshot
Support for multiple classes of traffic in multicomputer routers
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QNoC: QoS architecture and design process for network on chip
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/date.2003.1253633openalex-snapshot
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/date.2004.1269001openalex-snapshot
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
inferredcites →https://doi.org/10.1109/fpt.2004.1393315openalex-snapshot
Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture
inferredcites →https://doi.org/10.1109/fpt.2004.1393319openalex-snapshot
Implementation of a flexible RAKE receiver in heterogeneous reconfigurable hardware
inferredcites →https://doi.org/10.1109/icvd.2004.1261037openalex-snapshot
On-chip networks: a scalable, communication-centric embedded system design paradigm
inferredcites →https://doi.org/10.1109/ipdps.2003.1213180openalex-snapshot
SoCBUS: switched network on chip for hard real time embedded systems
inferredcites →https://doi.org/10.1109/ipdps.2004.1303131openalex-snapshot
Implementation of a HiperLAN/2 receiver on the reconfigurable Montium architecture
inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot
Æthereal Network on Chip:Concepts, Architectures, and Implementations
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/socc.2004.1362438openalex-snapshot
A virtual channel router for on-chip networks
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm
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Providing QoS Guarantees in a NoC by Virtual Channel Reservation
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Reconfigurable Networks-on-Chip
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Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections
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Smart Chips for Smart Surroundings – 4S
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Dynamic virtual channel routers with congestion awareness††Part of this research was first presented at the 45th Design Automation Conference (DAC-2008) [19] and the 29th International Conference of Computer Design (ICCD-2011) [33].
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Mach–Zehnder wavelength selective switch embedded with microring resonators
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Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.