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Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.vlsi.2009.01.002openalex-snapshot
A variable frequency link for a power-aware network-on-chip (NoC)
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/aspdac.2012.6164982openalex-snapshot
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs
inferredcites →https://doi.org/10.1109/date.2005.36openalex-snapshot
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip
inferredcites →https://doi.org/10.1109/date.2009.5090700openalex-snapshot
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
inferredcites →https://doi.org/10.1109/dsd.2008.64openalex-snapshot
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching
inferredcites →https://doi.org/10.1109/hpca.2003.1183527openalex-snapshot
Dynamic voltage scaling with links for power optimization of interconnection networks
inferredcites →https://doi.org/10.1109/hpca.2013.6522334openalex-snapshot
Breaking the on-chip latency barrier using SMART
inferredcites →https://doi.org/10.1109/iccd.2007.4601881openalex-snapshot
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/ipdps.2005.95openalex-snapshot
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
inferredcites →https://doi.org/10.1109/islped.2011.5993674openalex-snapshot
NoC frequency scaling with flexible-pipeline routers
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/jssc.2007.910957openalex-snapshot
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot
Æthereal Network on Chip:Concepts, Architectures, and Implementations
inferredcites →https://doi.org/10.1109/micro.2010.50openalex-snapshot
Throughput-Effective On-Chip Networks for Manycore Accelerators
inferredcites →https://doi.org/10.1109/nocs.2007.6openalex-snapshot
A Power and Energy Exploration of Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/recosoc.2011.5981514openalex-snapshot
A SDM-TDM based circuit-switched router for on-chip networks
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1669112.1669151openalex-snapshot
A case for dynamic frequency tuning in on-chip networks
inferredcites →https://doi.org/10.1145/2212908.2212933openalex-snapshot
Concurrent hybrid switching for massively parallel systems-on-chip
inferredcites →https://doi.org/10.1145/2228360.2228430openalex-snapshot
Explicit modeling of control and data for improved NoC router estimation
inferredcites →https://doi.org/10.1145/2333660.2333675openalex-snapshot
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems
inferredcites →https://doi.org/10.1155/2012/474765openalex-snapshot
Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks
inferredcites →https://doi.org/10.5555/1874620.1874758openalex-snapshot
A hybrid packet-circuit switched on-chip network based on SDM
inferredcites →https://doi.org/10.5555/2016802.2016897openalex-snapshot
NoC frequency scaling with flexible-pipeline routers
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-18656-2_3openalex-snapshot
A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC
inferred← citeshttps://doi.org/10.1007/978-3-031-28816-6_5openalex-snapshot
A Survey of On-Chip Hybrid Interconnect for Multicore Architectures
inferred← citeshttps://doi.org/10.1007/s11227-023-05700-7openalex-snapshot
TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architectures
inferred← citeshttps://doi.org/10.1016/bs.adcom.2021.09.001openalex-snapshot
Traffic-load-aware virtual channel power-gating in network-on-chips
inferred← citeshttps://doi.org/10.1016/j.micpro.2022.104712openalex-snapshot
Enabling circuit-switching in modern on-chip networks
inferred← citeshttps://doi.org/10.1049/iet-cta.2019.0853openalex-snapshot
Stability and stabilisation of heterogeneous switched systems with arbitrary switching constraints
inferred← citeshttps://doi.org/10.1109/ancs.2019.8901890openalex-snapshot
A Low-Cost and Energy-Efficient NoC Architecture for GPGPUs
inferred← citeshttps://doi.org/10.1109/fpl.2016.7577378openalex-snapshot
XNoC: A non-intrusive TDM circuit-switched Network-on-Chip
inferred← citeshttps://doi.org/10.1109/fpt.2016.7929522openalex-snapshot
Hybrid hard NoCs for efficient FPGA communication
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00074openalex-snapshot
Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing
inferred← citeshttps://doi.org/10.1109/icctct.2018.8551009openalex-snapshot
A Review on Hybrid Network on Chip
inferred← citeshttps://doi.org/10.1109/icssas66150.2025.11081083openalex-snapshot
Latency and Throughput Analysis in 3D NoC Design for Streaming Platform
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.87openalex-snapshot
ARTNoCs: An Evaluation Framework for Hardware Architectures of Real-Time NoCs
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00030openalex-snapshot
Dark-Silicon Inspired Energy Efficient Hierarchical TDM NoC
inferred← citeshttps://doi.org/10.1109/isvlsi49217.2020.00062openalex-snapshot
A Low-Cost Conflict-Free NoC Architecture for Heterogeneous Multicore Systems
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00018openalex-snapshot
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
inferred← citeshttps://doi.org/10.1109/nocs.2016.7579320openalex-snapshot
PROSA: protocol-driven NoC architecture
inferred← citeshttps://doi.org/10.1109/nocs50636.2020.9241583openalex-snapshot
In-Network Memory Access Ordering for Heterogeneous Multicore Systems
inferred← citeshttps://doi.org/10.1109/norcas51424.2020.9264993openalex-snapshot
Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs
inferred← citeshttps://doi.org/10.1109/norchip.2017.8124947openalex-snapshot
A call-up for circuit-switched NoCs in the Dark-Silicon Era
inferred← citeshttps://doi.org/10.1109/pdp52278.2021.00039openalex-snapshot
Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks
inferred← citeshttps://doi.org/10.1109/sbcci50935.2020.9189924openalex-snapshot
Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism
inferred← citeshttps://doi.org/10.1109/sbcci55532.2022.9893222openalex-snapshot
Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models
inferred← citeshttps://doi.org/10.1109/tc.2016.2643668openalex-snapshot
HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures
inferred← citeshttps://doi.org/10.1109/tc.2020.3013567openalex-snapshot
Power-Efficient Heterogeneous Many-Core Design With NCFET Technology
inferred← citeshttps://doi.org/10.1109/tpds.2016.2623619openalex-snapshot
Survey on Real-Time Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tpds.2017.2783337openalex-snapshot
Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tpds.2017.2784422openalex-snapshot
PROSA: Protocol-Driven Network on Chip Architecture
inferred← citeshttps://doi.org/10.1109/tpds.2019.2942589openalex-snapshot
HPPT-NoC: A Dark-Silicon Inspired Hierarchical TDM NoC with Efficient Power-Performance Trading
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2016.7753550openalex-snapshot
Opportunistic circuit-switching for energy efficient on-chip networks
inferred← citeshttps://doi.org/10.1145/2744769.2744879openalex-snapshot
On-chip interconnection network for accelerator-rich architectures
inferred← citeshttps://doi.org/10.1145/3307650.3322235openalex-snapshot
Adaptive memory-side last-level GPU caching
inferred← citeshttps://doi.org/10.1145/3386263.3406934openalex-snapshot
Energy-Efficient On-Chip Networks through Profiled Hybrid Switching
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
inferred← citeshttps://doi.org/10.4995/thesis/10251/107336openalex-snapshot
Improving Network-on-Chip Performance in Multi-Core Systems
inferred← citeshttps://doi.org/10.5555/2755753.2757164openalex-snapshot
An energy-efficient virtual channel power-gating mechanism for on-chip networks
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