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Improving cache locality for thread-level speculation

https://doi.org/10.1109/ipdps.2006.1639271

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/12.381947openalex-snapshot

Effective hardware-based data prefetching for high-performance processors

inferredcites →https://doi.org/10.1109/12.795218openalex-snapshot

A chip-multiprocessor architecture with speculative multithreading

inferredcites →https://doi.org/10.1109/hpca.1998.650559openalex-snapshot

Speculative versioning cache

inferredcites →https://doi.org/10.1109/icpp.1993.92openalex-snapshot

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

inferredcites →https://doi.org/10.1109/isca.1994.288164openalex-snapshot

Evaluating stream buffers as a secondary cache replacement

inferredcites →https://doi.org/10.1109/isca.1995.524548openalex-snapshot

Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors

inferredcites →https://doi.org/10.1109/micro.1992.697004openalex-snapshot

Stride Directed Prefetching In Scalar Processors

inferredcites →https://doi.org/10.1145/1082469.1082471openalex-snapshot

The STAMPede approach to thread-level speculation

inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot

A data locality optimizing algorithm

inferredcites →https://doi.org/10.1145/195473.195557openalex-snapshot

Compiler optimizations for improving data locality

inferredcites →https://doi.org/10.1145/277830.277850openalex-snapshot

Speculative multithreaded processors

inferredcites →https://doi.org/10.1145/291069.291020openalex-snapshot

Data speculation support for a chip multiprocessor

inferredcites →https://doi.org/10.1145/339647.339669openalex-snapshot

Selective, accurate, and timely self-invalidation using last-touch prediction

inferredcites →https://doi.org/10.1145/379240.379250openalex-snapshot

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors

inferredcites →https://doi.org/10.5555/977395.977665openalex-snapshot

Physical experimentation with prefetching helper threads on Intel's hyper-threaded processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11758525_68openalex-snapshot

Analysis of the Spatial and Temporal Locality in Data Accesses

inferred← citeshttps://doi.org/10.1007/978-3-540-69303-1_7openalex-snapshot

CMP Cache Architecture and the OpenMP Performance

inferred← citeshttps://doi.org/10.1007/978-3-540-74466-5_7openalex-snapshot

A Profiling Tool for Detecting Cache-Critical Data Structures

inferred← citeshttps://doi.org/10.1007/s10766-008-0075-4openalex-snapshot

Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems

inferred← citeshttps://doi.org/10.1109/cyberc.2012.59openalex-snapshot

Optimization of Automatic Conversion of Serial C to Parallel OpenMP

inferred← citeshttps://doi.org/10.1109/hpca.2011.5749728openalex-snapshot

Fast thread migration via cache working set prediction

inferred← citeshttps://doi.org/10.1109/isca.2006.43openalex-snapshot

Tolerating Dependences Between Large Speculative Threads Via Sub-Threads

inferred← citeshttps://doi.org/10.1109/micro.2016.7783708openalex-snapshot

Data-centric execution of speculative parallel programs

inferred← citeshttps://doi.org/10.1109/tpds.2007.1081openalex-snapshot

CMP Support for Large and Dependent Speculative Threads

inferred← citeshttps://doi.org/10.1145/1150019.1136504openalex-snapshot

Tolerating Dependences Between Large Speculative Threads Via Sub-Threads

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