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Tolerating Dependences Between Large Speculative Threads Via Sub-Threads

https://doi.org/10.1109/isca.2006.43
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot
The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/40.848474openalex-snapshot
The Stanford Hydra CMP
inferredcites →https://doi.org/10.1109/hpca.1998.650559openalex-snapshot
Speculative versioning cache
inferredcites →https://doi.org/10.1109/hpca.1999.744351openalex-snapshot
Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2002.995697openalex-snapshot
Eliminating squashes through learning cross-thread violations in speculative parallelization for multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2002.995699openalex-snapshot
Improving value communication for thread-level speculation
inferredcites →https://doi.org/10.1109/hpca.2003.1183537openalex-snapshot
Tradeoffs in buffering memory state for thread-level speculation in multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2004.10008openalex-snapshot
Out-of-Order Commit Processors
inferredcites →https://doi.org/10.1109/hpca.2005.22openalex-snapshot
Multithreaded Value Prediction
inferredcites →https://doi.org/10.1109/icde.2005.78openalex-snapshot
Improving Preemptive Prioritization via Statistical Characterization of OLTP Locking
inferredcites →https://doi.org/10.1109/ipdps.2006.1639271openalex-snapshot
Improving cache locality for thread-level speculation
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/micro.2002.1176234openalex-snapshot
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
inferredcites →https://doi.org/10.1109/micro.2003.1253246openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
inferredcites →https://doi.org/10.1109/micro.2005.28openalex-snapshot
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
inferredcites →https://doi.org/10.1145/1024393.1024395openalex-snapshot
Programming with transactional coherence and consistency (TCC)
inferredcites →https://doi.org/10.1145/223982.224451openalex-snapshot
Multiscalar processors
inferredcites →https://doi.org/10.1145/339647.339650openalex-snapshot
A scalable approach to thread-level speculation
inferredcites →https://doi.org/10.1145/339647.363382openalex-snapshot
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/379240.379264openalex-snapshot
Removing architectural bottlenecks to the scalability of speculative parallelization
inferredcites →https://doi.org/10.1145/605397.605416openalex-snapshot
Compiler optimization of scalar value communication between speculative threads
inferredcites →https://doi.org/10.1145/781498.781500openalex-snapshot
Using thread-level speculation to simplify manual parallelization
inferredcites →https://doi.org/10.1184/r1/6608174openalex-snapshot
Optimistic Intra-Transaction Parallelism on Chip Multiprocessors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11945918_19openalex-snapshot
Supporting Speculative Multithreading on Simultaneous Multithreaded Processors
inferred← citeshttps://doi.org/10.1007/978-3-642-19448-1_14openalex-snapshot
Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems
inferred← citeshttps://doi.org/10.1007/s10766-012-0210-0openalex-snapshot
Removal of Conflicts in Hardware Transactional Memory Systems
inferred← citeshttps://doi.org/10.1007/s44227-023-00013-wopenalex-snapshot
Performance Evaluation on Parallel Speculation-Based Construction of a Binary Search Tree
inferred← citeshttps://doi.org/10.1109/iiswc.2010.5649169openalex-snapshot
Toward a more accurate understanding of the limits of the TLS execution paradigm
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536249openalex-snapshot
Intermediate checkpointing with conflicting access prediction in transactional memory systems
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00024openalex-snapshot
T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware
inferred← citeshttps://doi.org/10.1109/snpd-summer57817.2022.00021openalex-snapshot
Parallel Binary Search Tree Construction Inspired by Thread-Level Speculation
inferred← citeshttps://doi.org/10.1145/1250727.1250732openalex-snapshot
A compiler cost model for speculative parallelization
inferred← citeshttps://doi.org/10.1145/1328671.1328673openalex-snapshot
Incrementally parallelizing database transactions with thread-level speculation
inferred← citeshttps://doi.org/10.1145/1401890.1401949openalex-snapshot
Cut-and-stitch
inferred← citeshttps://doi.org/10.1145/1542275.1542333openalex-snapshot
Combining thread level speculation helper threads and runahead execution
inferred← citeshttps://doi.org/10.1145/2400682.2400701openalex-snapshot
An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2400682.2400717openalex-snapshot
SCIN-cache
inferred← citeshttps://doi.org/10.1145/2938369openalex-snapshot
A Survey on Thread-Level Speculation Techniques
inferred← citeshttps://doi.org/10.1145/3468081.3471120openalex-snapshot
Reducing the Repairing Penalty on Misspeculation in Thread-Level Speculation
inferred← citeshttps://doi.org/10.1145/3719655openalex-snapshot
LitTLS: Lightweight Thread-Level Speculation on Little Cores
inferred← citeshttps://doi.org/10.35376/10324/17459openalex-snapshot
Design and evaluation of a Thread-Level Speculation runtime library
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94982openalex-snapshot
Mitosis based speculative multithreaded architectures
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