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Using Memory Access Traces to Map Threads and Data on Hierarchical Multi-core Platforms
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11945918_35openalex-snapshot
Exploring Thread and Memory Placement on NUMA Architectures: Solaris and Linux, UltraSPARC/FirePlane and Opteron/HyperTransport
inferredcites →https://doi.org/10.1007/978-3-642-02303-3_7openalex-snapshot
Dynamic Task and Data Placement over NUMA Architectures: An OpenMP Runtime Perspective
inferredcites →https://doi.org/10.1007/s12532-009-0002-8openalex-snapshot
Blossom V: a new implementation of a minimum cost perfect matching algorithm
inferredcites →https://doi.org/10.1023/a:1019899812171openalex-snapshot
Runtime vs. Manual Data Distribution for Architecture-Agnostic Shared-Memory Programming Models
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/hpcc.2010.114openalex-snapshot
Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors
inferredcites →https://doi.org/10.1109/iscc.2009.5202271openalex-snapshot
Multi-core aware process mapping and its impact on communication overhead of parallel applications
inferredcites →https://doi.org/10.1109/mc.2010.60openalex-snapshot
Analyzing Parallel Programs with Pin
inferredcites →https://doi.org/10.1109/pact.2009.22openalex-snapshot
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System
inferredcites →https://doi.org/10.1109/sbac-pad.2009.16openalex-snapshot
Memory Affinity for Hierarchical Shared Memory Multiprocessors
inferredcites →https://doi.org/10.1109/spdp.1990.143503openalex-snapshot
The maximum weight perfect matching problem for complete weighted graphs is in PC
inferredcites →https://doi.org/10.1109/wscad-scc.2010.26openalex-snapshot
Process Mapping Based on Memory Access Traces
inferredcites →https://doi.org/10.1145/1366219.1366222openalex-snapshot
Data and thread affinity in openmp programs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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ComScribe: Identifying Intra-node GPU Communication
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Monitoring Collective Communication Among GPUs
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State-of-the-Art Sharing-Aware Mapping Methods
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MAP-numa: Access Patterns Used to Characterize the NUMA Memory Access Optimization Techniques and Algorithms
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HydraFS: an efficient NUMA-aware in-memory file system
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Trace-driven and processing time extensions for Noxim simulator
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SIMD parallel MCMC sampling with applications for big-data Bayesian analytics
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Adaptive thread mapping strategies for transactional memory applications
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Characterizing communication and page usage of parallel applications for thread and data mapping
inferred← citeshttps://doi.org/10.1016/j.procs.2013.05.201openalex-snapshot
Topology Aware Task Stealing for On-chip NUMA Multi-core Processors
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Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories
inferred← citeshttps://doi.org/10.1109/hipc56025.2022openalex-snapshot
2022 IEEE 29th International Conference on High Performance Computing, Data, and Analytics (HiPC)
inferred← citeshttps://doi.org/10.1109/hipc56025.2022.00040openalex-snapshot
COMPROF and COMPLACE: Shared-Memory Communication Profiling and Automated Thread Placement via Dynamic Binary Instrumentation
inferred← citeshttps://doi.org/10.1109/iccd.2014.6974731openalex-snapshot
Static thread mapping for NoCs via binary instrumentation traces
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Cache Topology Aware Mapping of Stream Processing Applications onto CMPs
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Characterizing Loop-Level Communication Patterns in Shared Memory
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Using the Translation Lookaside Buffer to Map Threads in Parallel Applications Based on Shared Memory
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An empirical study on performance evaluation of parallel architecture for web application services
inferred← citeshttps://doi.org/10.1109/lca.2015.2451172openalex-snapshot
Threads and Data Mapping: Affinity Analysis for Traffic Reduction
inferred← citeshttps://doi.org/10.1109/mcsoc.2016.15openalex-snapshot
A Data Locality and Memory Contention Analysis Method in Embedded NUMA Multi-core Systems
inferred← citeshttps://doi.org/10.1109/padsw.2014.7097832openalex-snapshot
Where Should The Threads Go? Leveraging Hierarchical Data Locality to Solve the Thread Affinity Dilemma
inferred← citeshttps://doi.org/10.1109/pdcat.2012.115openalex-snapshot
Quantitatively Measuring the Memory Locality Leakage on NUMA Systems Based on Instruction-Based-Sampling
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Understanding the Data Traffic of Uncore in Westmere NUMA Architecture
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PHLAME: Hierarchical Locality Exploitation Using the PGAS Model
inferred← citeshttps://doi.org/10.1109/sbesc.2017.20openalex-snapshot
Trace-Driven Extension for Noxim Simulator
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Adapt Burstable Containers to Variable CPU Resources
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Assessing Parallel Thread Mapping Approaches on Shared Memory SMT Architectures
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Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping
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Exploiting Hierarchical Locality in Deep Parallel Architectures
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Affinity-Based Thread and Data Mapping in Shared Memory Systems
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Unveiling Thread Communication Bottlenecks Using Hardware-Independent Metrics
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Hybrid Shared-aware Cache Coherence Transition Strategy
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Automatic task and data mapping in shared memory architectures
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A Multi-core Testbed on Desktop Computer for Research on Power/Thermal Aware Resource Management
inferred← citeshttps://doi.org/10.5753/ctd.2017.3461openalex-snapshot
Online Thread and Data Mapping Using the Memory Management Unit
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Optimisation de la performance des applications de mémoire transactionnelle sur des plates-formes multicoeurs : une approche basée sur l'apprentissage automatique
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Dynamic optimization of data-flow task-parallel applications for large-scale NUMA systems
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