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Using the Translation Lookaside Buffer to Map Threads in Parallel Applications Based on Shared Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Simics: A full system simulation platform
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OpenMP: an industry standard API for shared-memory programming
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Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors
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Starling: Minimizing Communication Overhead in Virtualized Computing Platforms Using Decentralized Affinity-Aware Migration
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PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors
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A communication characterisation of Splash-2 and Parsec
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An approach for matching communication patterns in parallel applications
inferredcites →https://doi.org/10.1109/ipdps.2010.5470442openalex-snapshot
Structuring the execution of OpenMP applications for multicore architectures
inferredcites →https://doi.org/10.1109/ipdps.2011.197openalex-snapshot
Using Memory Access Traces to Map Threads and Data on Hierarchical Multi-core Platforms
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2008.16openalex-snapshot
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
inferredcites →https://doi.org/10.1109/iscas.2001.922002openalex-snapshot
Modeling and verification of cache coherence protocols
inferredcites →https://doi.org/10.1109/iscc.2009.5202271openalex-snapshot
Multi-core aware process mapping and its impact on communication overhead of parallel applications
inferredcites →https://doi.org/10.1109/mc.2010.60openalex-snapshot
Analyzing Parallel Programs with Pin
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The maximum weight perfect matching problem for complete weighted graphs is in PC
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Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1394608.1382127openalex-snapshot
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
inferredcites →https://doi.org/10.1145/1531793.1531803openalex-snapshot
Enhancing operating system support for multicore processors by using hardware performance monitoring
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The NAS Parallel Benchmarks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Communication‐aware thread mapping using the translation lookaside buffer
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Sharing-Aware Mapping and Parallel Architectures
inferred← citeshttps://doi.org/10.1007/978-3-319-91074-1_3openalex-snapshot
Sharing-Aware Mapping and Parallel Applications
inferred← citeshttps://doi.org/10.1007/978-3-319-91074-1_4openalex-snapshot
State-of-the-Art Sharing-Aware Mapping Methods
inferred← citeshttps://doi.org/10.1016/j.jpdc.2013.11.006openalex-snapshot
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols
inferred← citeshttps://doi.org/10.1016/j.jpdc.2025.105145openalex-snapshot
Integration framework for online thread throttling with thread and page mapping on NUMA systems
inferred← citeshttps://doi.org/10.1016/j.parco.2015.01.005openalex-snapshot
Communication-aware process and thread mapping using online communication detection
inferred← citeshttps://doi.org/10.1016/j.parco.2021.102753openalex-snapshot
Context switch cost aware joint task merging and scheduling for deep learning applications
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Characterizing communication and page usage of parallel applications for thread and data mapping
inferred← citeshttps://doi.org/10.1109/hipc56025.2022openalex-snapshot
2022 IEEE 29th International Conference on High Performance Computing, Data, and Analytics (HiPC)
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COMPROF and COMPLACE: Shared-Memory Communication Profiling and Automated Thread Placement via Dynamic Binary Instrumentation
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Effective Exploration of Thread Throttling and Thread/Page Mapping on NUMA Systems
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Leveraging Hierarchical Data Locality in Parallel Programming Models
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DQN-Based Dynamic Query Optimization Method of Data Cross-Chain Based on Multi-channel Relay Chain
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Characterizing Loop-Level Communication Patterns in Shared Memory
inferred← citeshttps://doi.org/10.1109/ipdps.2013.57openalex-snapshot
Communication-Based Mapping Using Shared Pages
inferred← citeshttps://doi.org/10.1109/ipdpsw63119.2024.00202openalex-snapshot
Integration Framework for Online Thread Throttling with Thread and Page Mapping on NUMA Systems
inferred← citeshttps://doi.org/10.1109/padsw.2014.7097832openalex-snapshot
Where Should The Threads Go? Leveraging Hierarchical Data Locality to Solve the Thread Affinity Dilemma
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PHLAME: Hierarchical Locality Exploitation Using the PGAS Model
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Compiler support for selective page migration in NUMA architectures
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Exploiting Hierarchical Locality in Deep Parallel Architectures
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Affinity-Based Thread and Data Mapping in Shared Memory Systems
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Automatic task and data mapping in shared memory architectures
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A Multi-core Testbed on Desktop Computer for Research on Power/Thermal Aware Resource Management
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PampaAffinity: Otimização de Aplicações Paralelas via Ajuste Dinâmico e Transparente do Grau de Paralelismo e Mapeamento de Threads
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Runtime-assisted coherent caching
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