On the public citation graph
SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2007.346189openalex-snapshot
A Scalable, Non-blocking Approach to Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2007.346204openalex-snapshot
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
inferredcites →https://doi.org/10.1109/iiswc.2008.4636089openalex-snapshot
STAMP: Stanford Transactional Applications for Multi-Processing
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2008.17openalex-snapshot
Flexible Decoupled Transactional Memory Support
inferredcites →https://doi.org/10.1109/isscc.2008.4523067openalex-snapshot
A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor
inferredcites →https://doi.org/10.1109/micro.2010.23openalex-snapshot
A Dynamically Adaptable Hardware Transactional Memory
inferredcites →https://doi.org/10.1109/pact.2009.19openalex-snapshot
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
inferredcites →https://doi.org/10.1109/pdp.2008.63openalex-snapshot
Characterization of Conflicts in Log-Based Transactional Memory (LogTM)
inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferredcites →https://doi.org/10.1145/1073814.1073861openalex-snapshot
Advanced contention management for dynamic software transactional memory
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1229428.1229454openalex-snapshot
Efficient nonblocking software transactional memory
inferredcites →https://doi.org/10.1145/1250662.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferredcites →https://doi.org/10.1145/1394608.1382134openalex-snapshot
Flexible Decoupled Transactional Memory Support
inferredcites →https://doi.org/10.1145/1454456.1454464openalex-snapshot
Parallel Programming with Transactional Memory
inferredcites →https://doi.org/10.1145/1461928.1461943openalex-snapshot
Parallel programming with transactional memory
inferredcites →https://doi.org/10.1145/1509084.1509094openalex-snapshot
Version management alternatives for hardware transactional memory
inferredcites →https://doi.org/10.1145/1542275.1542299openalex-snapshot
Refereeing conflicts in hardware transactional memory
inferredcites →https://doi.org/10.1145/1854273.1854311openalex-snapshot
Discovering and understanding performance bottlenecks in transactional applications
inferredcites →https://doi.org/10.1145/1941553.1941579openalex-snapshot
Lock-free and scalable multi-version software transactional memory
inferredcites →https://doi.org/10.1145/2038037.1941579openalex-snapshot
Lock-free and scalable multi-version software transactional memory
inferredcites →https://doi.org/10.1145/362686.362692openalex-snapshot
Space/time trade-offs in hash coding with allowable errors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522346openalex-snapshot
In-network traffic regulation for Transactional Memory
inferred← citeshttps://doi.org/10.1109/iscas.2013.6571962openalex-snapshot
Implementation of hybrid version management in hardware transactional memory
inferred← citeshttps://doi.org/10.1109/pact.2019.00023openalex-snapshot
Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2021.3085210openalex-snapshot
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2022.3206777openalex-snapshot
LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager
inferred← citeshttps://doi.org/10.1145/2400682.2400701openalex-snapshot
An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2628071.2628076openalex-snapshot
Consolidated conflict detection for hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2779621openalex-snapshot
Supporting Time-Based QoS Requirements in Software Transactional Memory
inferred← citeshttps://doi.org/10.1145/2837028openalex-snapshot
A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution
inferred← citeshttps://doi.org/10.1145/2892208.2892227openalex-snapshot
Reducing memory buffering overhead in software thread-level speculation
inferred← citeshttps://doi.org/10.2991/isci-15.2015.204openalex-snapshot
Design and Implementation of Data Version Management Strategy Foresight in STM
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