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A Dynamically Adaptable Hardware Transactional Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2007.346189openalex-snapshot
A Scalable, Non-blocking Approach to Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2007.346204openalex-snapshot
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
inferredcites →https://doi.org/10.1109/iiswc.2008.4636089openalex-snapshot
STAMP: Stanford Transactional Applications for Multi-Processing
inferredcites →https://doi.org/10.1109/ipdps.2009.5161021openalex-snapshot
Speculation-based conflict resolution in hardware transactional memory
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2005.54openalex-snapshot
Virtualizing Transactional Memory
inferredcites →https://doi.org/10.1109/isca.2006.13openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1109/isca.2008.17openalex-snapshot
Flexible Decoupled Transactional Memory Support
inferredcites →https://doi.org/10.1109/micro.2006.9openalex-snapshot
Architectural Support for Software Transactional Memory
inferredcites →https://doi.org/10.1109/micro.2008.4771795openalex-snapshot
Dependence-aware transactional memory for increased concurrency
inferredcites →https://doi.org/10.1109/pact.2009.19openalex-snapshot
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferredcites →https://doi.org/10.1145/1073814.1073861openalex-snapshot
Advanced contention management for dynamic software transactional memory
inferredcites →https://doi.org/10.1145/1080695.1070011openalex-snapshot
Virtualizing Transactional Memory
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1150019.1136506openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1145/1250662.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferredcites →https://doi.org/10.1145/1394608.1382134openalex-snapshot
Flexible Decoupled Transactional Memory Support
inferredcites →https://doi.org/10.1145/1454115.1454137openalex-snapshot
Scalable and reliable communication for hardware transactional memory
inferredcites →https://doi.org/10.1145/146628.139709openalex-snapshot
Alternative implementations of two-level adaptive branch prediction
inferredcites →https://doi.org/10.1145/1542275.1542299openalex-snapshot
Refereeing conflicts in hardware transactional memory
inferredcites →https://doi.org/10.1145/285930.286004openalex-snapshot
Alternative implementations of two-level adaptive branch prediction
inferredcites →https://doi.org/10.1145/872035.872048openalex-snapshot
Software transactional memory for dynamic-sized data structures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4939-2092-1_27openalex-snapshot
Hardware Approaches to Transactional Memory in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/s11227-012-0854-yopenalex-snapshot
Improving performance of software transactional memory through contention locality
inferred← citeshttps://doi.org/10.1007/s11227-013-1072-yopenalex-snapshot
Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems
inferred← citeshttps://doi.org/10.1016/j.procs.2013.05.190openalex-snapshot
EcoTM: Conflict-aware Economical Unbounded Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.12.006openalex-snapshot
Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms
inferred← citeshttps://doi.org/10.1109/acit-csi.2015.38openalex-snapshot
Hardware Transactional Memory with Delayed-Committing
inferred← citeshttps://doi.org/10.1109/candar.2016.0026openalex-snapshot
A Concurrency Control in Hardware Transactional Memory Considering Execution Path Variation
inferred← citeshttps://doi.org/10.1109/fmcad.2015.7542247openalex-snapshot
Verification of cache coherence protocols wrt. trace filters
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522346openalex-snapshot
In-network traffic regulation for Transactional Memory
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00120openalex-snapshot
No Rush in Executing Atomic Instructions
inferred← citeshttps://doi.org/10.1109/icecs.2018.8618020openalex-snapshot
Isolation-Safe Speculative Access Control for Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/icis.2014.6912153openalex-snapshot
Dynamic data rebalancing in Hadoop
inferred← citeshttps://doi.org/10.1109/iiai-aai.2014.134openalex-snapshot
A Lazy-Updating Snoop Cache Protocol for Transactional Memory
inferred← citeshttps://doi.org/10.1109/ipdps.2012.19openalex-snapshot
SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory
inferred← citeshttps://doi.org/10.1109/ipdps.2012.22openalex-snapshot
SUV: A Novel Single-Update Version-Management Scheme for Hardware Transactional Memory Systems
inferred← citeshttps://doi.org/10.1109/ipdps.2014.69openalex-snapshot
Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/ipdps.2014.70openalex-snapshot
Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell
inferred← citeshttps://doi.org/10.1109/ipdps47924.2020.00027openalex-snapshot
Transaction-Based Core Reliability
inferred← citeshttps://doi.org/10.1109/ipdps57955.2024.00081openalex-snapshot
LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.320openalex-snapshot
On the Correctness of Mixing Lazy and Eager Version Management in Transactions
inferred← citeshttps://doi.org/10.1109/iscas.2013.6571962openalex-snapshot
Implementation of hybrid version management in hardware transactional memory
inferred← citeshttps://doi.org/10.1109/iscas.2014.6865741openalex-snapshot
Hardware transactional memory on multi-processor FPGA platform
inferred← citeshttps://doi.org/10.1109/lca.2018.2791433openalex-snapshot
Core Reliability: Leveraging Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/paap.2011.50openalex-snapshot
A Case Study of the Interplay between Conflict Management and Version Management in Hardware Transactional Memory Systems
inferred← citeshttps://doi.org/10.1109/pacrim.2017.8121912openalex-snapshot
Initial study of a phase-aware scheduling for hardware transactional memory
inferred← citeshttps://doi.org/10.1109/pact.2019.00023openalex-snapshot
Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/pdp55904.2022.00032openalex-snapshot
Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/snpd.2017.8022760openalex-snapshot
Performance evaluation of delayed-committing transactional memory
inferred← citeshttps://doi.org/10.1109/tc.2011.230openalex-snapshot
LS-Sig: Locality-Sensitive Signatures for Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2012.138openalex-snapshot
Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets
inferred← citeshttps://doi.org/10.1109/tpds.2013.262openalex-snapshot
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2021.3085210openalex-snapshot
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1145/2400682.2400701openalex-snapshot
An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2541228.2555299openalex-snapshot
Techniques to improve performance in requester-wins hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2628071.2628076openalex-snapshot
Consolidated conflict detection for hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2837028openalex-snapshot
A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution
inferred← citeshttps://doi.org/10.1145/2875425openalex-snapshot
Power Efficient Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1145/2892208.2892227openalex-snapshot
Reducing memory buffering overhead in software thread-level speculation
inferred← citeshttps://doi.org/10.11591/eecsi.1.409openalex-snapshot
Configurable Version Management Hardware Transactional Memory for Multi-processor Platform
inferred← citeshttps://doi.org/10.1587/transfun.e102.a.48openalex-snapshot
Multi-Service Oriented Stream Data Synchronization Scheme for Multicore Cipher Chips
inferred← citeshttps://doi.org/10.1587/transinf.2016pap0006openalex-snapshot
A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory
inferred← citeshttps://doi.org/10.4304/jcp.8.1.18-26openalex-snapshot
Using A Runtime to Overcome The Pathologies in Hardware Transactional Memory Systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94562openalex-snapshot
Architectural support for high-performing hardware transactional memory systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94566openalex-snapshot
Adaptive memory hierarchies for next generation tiled microarchitectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94989openalex-snapshot
Towards lightweight and high-performance hardware transactional memory
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95386openalex-snapshot
Techniques to improve concurrency in hardware transactional memory
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