On the public citation graph

Competitive Cache Replacement Strategies for Shared Cache Environments

0 signed · 37 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1006/jcss.1995.1021openalex-snapshot
Competitive Paging with Locality of Reference
inferredcites →https://doi.org/10.1007/bf01759073openalex-snapshot
A strongly competitive randomized paging algorithm
inferredcites →https://doi.org/10.1007/s00224-010-9273-8openalex-snapshot
The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation
inferredcites →https://doi.org/10.1016/0196-6774(91)90041-vopenalex-snapshot
Competitive paging algorithms
inferredcites →https://doi.org/10.1016/j.jpdc.2013.04.008openalex-snapshot
Oblivious algorithms for multicores and networks of processors
inferredcites →https://doi.org/10.1109/ipdps.2010.5470354openalex-snapshot
Oblivious algorithms for multicores and network of processors
inferredcites →https://doi.org/10.1109/isca.1988.5212openalex-snapshot
On the inclusion properties for multi-level cache hierarchies
inferredcites →https://doi.org/10.1109/isca.1994.288163openalex-snapshot
Tradeoffs in two-level on-chip caching
inferredcites →https://doi.org/10.1109/sfcs.1977.24openalex-snapshot
Probabilistic computations: Toward a unified measure of complexity
inferredcites →https://doi.org/10.1109/sfcs.1995.492477openalex-snapshot
Application-controlled paging for a shared cache
inferredcites →https://doi.org/10.1137/s0097539797324278openalex-snapshot
Application-Controlled Paging for a Shared Cache
inferredcites →https://doi.org/10.1145/103418.103422openalex-snapshot
Competitive paging with locality of reference
inferredcites →https://doi.org/10.1145/106972.106979openalex-snapshot
Software prefetching
inferredcites →https://doi.org/10.1145/143365.143488openalex-snapshot
Design and evaluation of a compiler algorithm for prefetching
inferredcites →https://doi.org/10.1145/1669112.1669165openalex-snapshot
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems
inferredcites →https://doi.org/10.1145/1989493.1989513openalex-snapshot
Brief announcement
inferredcites →https://doi.org/10.1145/2786.2793openalex-snapshot
Amortized efficiency of list update and paging rules
inferredcites →https://doi.org/10.1145/285930.285954openalex-snapshot
Retrospective: on the inclusion properties for multi-level cache hierarchies
inferredcites →https://doi.org/10.1145/285930.285994openalex-snapshot
On the inclusion properties for multi-level cache hierarchies
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4939-2864-4_534openalex-snapshot
Analyzing Cache Behaviour in Multicore Architectures
inferred← citeshttps://doi.org/10.1007/978-3-642-27848-8_534-1openalex-snapshot
Analyzing Cache Behaviour in Multicore Architectures
inferred← citeshttps://doi.org/10.1016/j.ipl.2018.10.012openalex-snapshot
Upper bounds for multi-level multi-server paging
inferred← citeshttps://doi.org/10.1109/hipc.2017.00023openalex-snapshot
Provably Efficient Scheduling of Dynamically Allocating Programs on Parallel Cache Hierarchies
inferred← citeshttps://doi.org/10.1109/isvlsi.2017.40openalex-snapshot
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor
inferred← citeshttps://doi.org/10.1137/1.9781611973402.71openalex-snapshot
Cache-Adaptive Algorithms
inferred← citeshttps://doi.org/10.1137/1.9781611976465.180openalex-snapshot
Tight Bounds for Parallel Paging and Green Paging
inferred← citeshttps://doi.org/10.1137/1.9781611976489.1openalex-snapshot
Beyond Worst-case Analysis of Multicore Caching Strategies
inferred← citeshttps://doi.org/10.1145/2612669.2612703openalex-snapshot
Persistent unfairness arising from cache residency imbalance
inferred← citeshttps://doi.org/10.1145/3350755.3400231openalex-snapshot
Green Paging and Parallel Paging
inferred← citeshttps://doi.org/10.1145/3350755.3400233openalex-snapshot
How to Manage High-Bandwidth Memory Automatically
inferred← citeshttps://doi.org/10.1145/3350755.3400274openalex-snapshot
Closing the Gap Between Cache-oblivious and Cache-adaptive Analysis
inferred← citeshttps://doi.org/10.1145/3458817.3476181openalex-snapshot
Clairvoyant prefetching for distributed machine learning I/O
inferred← citeshttps://doi.org/10.1145/3490148.3538570openalex-snapshot
Automatic HBM Management
inferred← citeshttps://doi.org/10.1145/3490148.3538577openalex-snapshot
Online Parallel Paging with Optimal Makespan
inferred← citeshttps://doi.org/10.1145/3694906.3743336openalex-snapshot
Managing High-Bandwidth Memory is a Parallel Scheduling Problem (full paper only)
inferred← citeshttps://doi.org/10.5555/2634074.2634145openalex-snapshot
Cache-adaptive algorithms
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.