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Software prefetching
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0096-0551(81)90048-5openalex-snapshot
Register allocation via coloring
inferredcites →https://doi.org/10.1109/mc.1987.1663695openalex-snapshot
A Survey of RISC Processors and Computers of the Mid-1980s
inferredcites →https://doi.org/10.1145/100215.100233openalex-snapshot
Analyzing and visualizing performance of memory hierarchies
inferredcites →https://doi.org/10.1145/1296930.1296931openalex-snapshot
Performance of various computers using standard linear equations software in a Fortran environment
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/800230.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/872726.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.5555/110382.110587openalex-snapshot
Data cache performance of supercomputer applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781119332015.ch1openalex-snapshot
Multi‐ and Many‐Cores, Architectural Overview for Programmers
inferred← citeshttps://doi.org/10.1002/asi.21489openalex-snapshot
Hip and trendy: Characterizing emerging trends on Twitter
inferred← citeshttps://doi.org/10.1002/cpe.851openalex-snapshot
Recurrence analysis for effective array prefetching in Java
inferred← citeshttps://doi.org/10.1006/jpdc.1996.0036openalex-snapshot
Integrating Fine-Grained Message Passing in Cache Coherent Shared Memory Multiprocessors
inferred← citeshttps://doi.org/10.1006/jpdc.1996.0109openalex-snapshot
Evaluating the Performance of Multithreading and Prefetching in Multiprocessors
inferred← citeshttps://doi.org/10.1006/jpdc.1999.1553openalex-snapshot
Software Data Prefetching for Software Pipelined Loops
inferred← citeshttps://doi.org/10.1006/jpdc.1999.1606openalex-snapshot
Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols
inferred← citeshttps://doi.org/10.1007/11572961_20openalex-snapshot
Improving the Performance of GCC by Exploiting IA-64 Architectural Features
inferred← citeshttps://doi.org/10.1007/11575832_11openalex-snapshot
Cache-Conscious Collision Resolution in String Hash Tables
inferred← citeshttps://doi.org/10.1007/3-540-44520-x_31openalex-snapshot
Load Scheduling with Profile Information
inferred← citeshttps://doi.org/10.1007/3-540-44570-6_3openalex-snapshot
Content-Based Prefetching: Initial Results
inferred← citeshttps://doi.org/10.1007/3-540-45706-2_66openalex-snapshot
Runtime Association of Software Prefetch Control to Memory Access Instructions
inferred← citeshttps://doi.org/10.1007/3-540-45937-5_22openalex-snapshot
Value-Profile Guided Stride Prefetching for Irregular Code
inferred← citeshttps://doi.org/10.1007/3-540-47847-7_15openalex-snapshot
A Programmable Memory Hierarchy for Prefetching Linked Data Structures
inferred← citeshttps://doi.org/10.1007/3-540-55984-1_18openalex-snapshot
Register pipelining: An integrated approach to register allocation for scalar and subscripted variables
inferred← citeshttps://doi.org/10.1007/3-540-57818-8_63openalex-snapshot
A multi-threaded architecture for prefetching in object bases
inferred← citeshttps://doi.org/10.1007/3-540-57840-4_26openalex-snapshot
Increasing memory bandwidth for vector computations
inferred← citeshttps://doi.org/10.1007/3-540-63138-0_16openalex-snapshot
Improving cache performance through tiling and data alignment
inferred← citeshttps://doi.org/10.1007/978-1-4419-8987-1_14openalex-snapshot
Bandwidth-Based Prefetching for Constant-Stride Arrays
inferred← citeshttps://doi.org/10.1007/978-1-4615-2698-8_8openalex-snapshot
Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors
inferred← citeshttps://doi.org/10.1007/978-1-4615-3164-7openalex-snapshot
Compiling Parallel Loops for High Performance Computers
inferred← citeshttps://doi.org/10.1007/978-1-4757-3337-2_4openalex-snapshot
Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches
inferred← citeshttps://doi.org/10.1007/978-3-030-67667-4_26openalex-snapshot
Learning I/O Access Patterns to Improve Prefetching in SSDs
inferred← citeshttps://doi.org/10.1007/978-3-031-83796-8_18openalex-snapshot
File Prefetching Accuracy Enhancement Using Deep Learning Approaches
inferred← citeshttps://doi.org/10.1007/978-3-319-10214-6_6openalex-snapshot
Characterizing the Impact of Prefetching on Scientific Application Performance
inferred← citeshttps://doi.org/10.1007/978-3-319-10705-9_58openalex-snapshot
Unveiling WARIS Code, a Parallel and Multi-purpose FDM Framework
inferred← citeshttps://doi.org/10.1007/978-3-540-30501-9_20openalex-snapshot
The Practice of I/O Optimizations for Out-of-Core Computation
inferred← citeshttps://doi.org/10.1007/978-3-540-49051-7_18openalex-snapshot
Virtual Cache Line: A New Technique to Improve Cache Exploitation for Recursive Data Structures
inferred← citeshttps://doi.org/10.1007/978-3-540-71229-9_4openalex-snapshot
Using Prefetching to Improve Reference-Counting Garbage Collectors
inferred← citeshttps://doi.org/10.1007/978-3-540-72521-3_6openalex-snapshot
Dependence-Based Code Generation for a CELL Processor
inferred← citeshttps://doi.org/10.1007/978-3-540-72685-2_20openalex-snapshot
Power-Aware Software Prefetching
inferred← citeshttps://doi.org/10.1007/978-3-642-14390-8_52openalex-snapshot
Introducing the Semi-stencil Algorithm
inferred← citeshttps://doi.org/10.1007/978-3-642-28293-5_17openalex-snapshot
New Memory Organizations for 3D DRAM and PCMs
inferred← citeshttps://doi.org/10.1007/978-3-642-36424-2_6openalex-snapshot
A Multi-core Memory Organization for 3-D DRAM as Main Memory
inferred← citeshttps://doi.org/10.1007/978-3-642-59686-5_46openalex-snapshot
KaHPF: Compiler generated Data Prefetching for HPF
inferred← citeshttps://doi.org/10.1007/bf02109380openalex-snapshot
Optimizing throughput and resource utilization using pipelining: Transformation based approach
inferred← citeshttps://doi.org/10.1007/bf02366568openalex-snapshot
Performance enhancement methods for parallel programs with multilevel memory
inferred← citeshttps://doi.org/10.1007/bfb0020457openalex-snapshot
Bounds on memory bandwidth in streamed computations
inferred← citeshttps://doi.org/10.1007/bfb0020473openalex-snapshot
Efficient software data prefetching for a Loop with large arrays
inferred← citeshttps://doi.org/10.1007/bfb0037203openalex-snapshot
Data prefetching for non-linear memory references
inferred← citeshttps://doi.org/10.1007/pl00010673openalex-snapshot
View management in multimedia databases
inferred← citeshttps://doi.org/10.1007/s00778-006-0025-yopenalex-snapshot
Cache-conscious frequent pattern mining on modern and emerging processors
inferred← citeshttps://doi.org/10.1007/s00778-010-0183-9openalex-snapshot
Engineering scalable, cache and space efficient tries for strings
inferred← citeshttps://doi.org/10.1007/s10617-010-9058-yopenalex-snapshot
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions
inferred← citeshttps://doi.org/10.1007/s11265-005-6650-7openalex-snapshot
Memory Performance Optimizations For Real-Time Software HDTV Decoding
inferred← citeshttps://doi.org/10.1007/s11265-014-0881-4openalex-snapshot
A Novel Object-Oriented Software Cache for Scratchpad-Based Multi-Core Clusters
inferred← citeshttps://doi.org/10.1007/s11390-010-9320-6openalex-snapshot
Managing Data-Objects in Dynamically Reconfigurable Caches
inferred← citeshttps://doi.org/10.1016/0165-6074(95)00003-7openalex-snapshot
A software-controlled prefetching mechanism for software-managed TLBs
inferred← citeshttps://doi.org/10.1016/0167-739x(94)00067-oopenalex-snapshot
Implementation and evaluation of update-based cache protocols under relaxed memory consistency models
inferred← citeshttps://doi.org/10.1016/0167-739x(95)00022-kopenalex-snapshot
Software assistance for data caches
inferred← citeshttps://doi.org/10.1016/0743-7315(92)90050-wopenalex-snapshot
Compile-time optimization of near-neighbor communication for scalable shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1016/j.future.2014.10.024openalex-snapshot
Towards an efficient storage and retrieval mechanism for large unstructured grids
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.02.008openalex-snapshot
A novel hardware support for heterogeneous multi-core memory system
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.09.004openalex-snapshot
TELEPORT: Hardware/software alternative to CUDA shared memory programming
inferred← citeshttps://doi.org/10.1016/j.peva.2004.10.018openalex-snapshot
On the performance of trace locality of reference
inferred← citeshttps://doi.org/10.1016/j.softx.2017.07.004openalex-snapshot
Rambrain - a library for virtually extending physical memory
inferred← citeshttps://doi.org/10.1016/j.sysarc.2005.05.002openalex-snapshot
Pattern-driven prefetching for multimedia applications on embedded processors
inferred← citeshttps://doi.org/10.1016/s0004-3702(00)00082-5openalex-snapshot
Principles and applications of continual computation
inferred← citeshttps://doi.org/10.1016/s0141-9331(99)00011-3openalex-snapshot
Secondary cache enhancement using a novel tagged prefetching method
inferred← citeshttps://doi.org/10.1016/s1383-7621(02)00122-4openalex-snapshot
Increasing hardware data prefetching performance using the second-level cache
inferred← citeshttps://doi.org/10.1016/s1383-7621(98)00012-5openalex-snapshot
Combining data prefetching with non-blocking loads to alleviate cache pollution effects
inferred← citeshttps://doi.org/10.1016/s1383-7621(98)00048-4openalex-snapshot
DataScalar: A memory-centric approach to computing
inferred← citeshttps://doi.org/10.1023/a:1007952919024openalex-snapshot
Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems
inferred← citeshttps://doi.org/10.1023/a:1008119209479openalex-snapshot
Source-to-Source Instrumentation for the Optimization of an Automatic Reading System
inferred← citeshttps://doi.org/10.1023/a:1018792002672openalex-snapshot
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors1
inferred← citeshttps://doi.org/10.1023/a:1024556711058openalex-snapshot
Restructuring Computations for Temporal Data Cache Locality
inferred← citeshttps://doi.org/10.1023/b:ijpp.0000042082.31819.6dopenalex-snapshot
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures
inferred← citeshttps://doi.org/10.1093/comjnl/bxv112openalex-snapshot
Why Does Data Prefetching Not Work for Modern Workloads?
inferred← citeshttps://doi.org/10.1109/12.677225openalex-snapshot
CPU cache prefetching: Timing evaluation of hardware implementations
inferred← citeshttps://doi.org/10.1109/12.752654openalex-snapshot
Automatic compiler-inserted prefetching for pointer-based applications
inferred← citeshttps://doi.org/10.1109/12.752659openalex-snapshot
Effects of multithreading on cache performance
inferred← citeshttps://doi.org/10.1109/12.811113openalex-snapshot
Active management of data caches by exploiting reuse information
inferred← citeshttps://doi.org/10.1109/12.895941openalex-snapshot
Dynamic access ordering for streamed computations
inferred← citeshttps://doi.org/10.1109/32.392982openalex-snapshot
Performance characterization of optimizing compilers
inferred← citeshttps://doi.org/10.1109/43.543768openalex-snapshot
Elimination of redundant memory traffic in high-level synthesis
inferred← citeshttps://doi.org/10.1109/5.747863openalex-snapshot
Cache-coherent distributed shared memory: perspectives on its development and future challenges
inferred← citeshttps://doi.org/10.1109/71.285604openalex-snapshot
The impact of parallel loop scheduling strategies on prefetching in a shared memory multiprocessor
inferred← citeshttps://doi.org/10.1109/71.395402openalex-snapshot
Sequential hardware prefetching in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1109/71.762818openalex-snapshot
A general interprocedural framework for placement of split-phase large latency operations
inferred← citeshttps://doi.org/10.1109/78.824694openalex-snapshot
Real-time sonar beamforming on workstations using process networks and POSIX threads
inferred← citeshttps://doi.org/10.1109/79.664698openalex-snapshot
The latest word in digital and media processing
inferred← citeshttps://doi.org/10.1109/88.218177openalex-snapshot
Optimizing a superscalar machine to run vector code
inferred← citeshttps://doi.org/10.1109/acssc.1998.751620openalex-snapshot
Real-time sonar beamforming on a Unix workstation using process networks and POSIX threads
inferred← citeshttps://doi.org/10.1109/acssc.1999.832310openalex-snapshot
Real-time high-throughput sonar beamforming kernels using native signal processing and memory latency hiding techniques
inferred← citeshttps://doi.org/10.1109/afrcon.2013.6757732openalex-snapshot
Pre-fetching techniques for effective web latency reduction — A survey
inferred← citeshttps://doi.org/10.1109/aispas.1997.581667openalex-snapshot
Prefetching by self-contained variables-a generalization from array to recursive data structures
inferred← citeshttps://doi.org/10.1109/asap.1992.218549openalex-snapshot
Matrix computations in arrays of DSPs
inferred← citeshttps://doi.org/10.1109/asap.2014.6868666openalex-snapshot
Exploring DMA-assisted prefetching strategies for software caches on multicore clusters
inferred← citeshttps://doi.org/10.1109/bigdata.2013.6691578openalex-snapshot
Iteration aware prefetching for unstructured grids
inferred← citeshttps://doi.org/10.1109/camp.1995.521039openalex-snapshot
Software data prefetching to reduce data reloading overhead
inferred← citeshttps://doi.org/10.1109/cgo.2006.4openalex-snapshot
A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework
inferred← citeshttps://doi.org/10.1109/cgo.2017.7863749openalex-snapshot
Software prefetching for indirect memory accesses
inferred← citeshttps://doi.org/10.1109/cmpcon.1994.282946openalex-snapshot
A PA-RISC microprocessor PA/50L for low-cost systems
inferred← citeshttps://doi.org/10.1109/date.2001.915120openalex-snapshot
Access pattern based local memory customization for low power embedded systems
inferred← citeshttps://doi.org/10.1109/date.2008.4484840openalex-snapshot
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
inferred← citeshttps://doi.org/10.1109/fpt.2005.1568552openalex-snapshot
Compiler-directed design space exploration for caching and prefetching data in high-level synthesis
inferred← citeshttps://doi.org/10.1109/hicss.1994.323142openalex-snapshot
Experimental implementation of dynamic access ordering
inferred← citeshttps://doi.org/10.1109/hicss.1995.375390openalex-snapshot
A comparative evaluation of software techniques to hide memory latency
inferred← citeshttps://doi.org/10.1109/hicss.1995.375393openalex-snapshot
Reducing memory latency using a small software driven array cache
inferred← citeshttps://doi.org/10.1109/hicss.1996.495453openalex-snapshot
Data prefetching for distributed shared memory systems
inferred← citeshttps://doi.org/10.1109/hicss.1998.649285openalex-snapshot
Software prefetching for software pipelined loops
inferred← citeshttps://doi.org/10.1109/hipc.1998.737965openalex-snapshot
Precise control of instruction caches
inferred← citeshttps://doi.org/10.1109/hipc.1998.737967openalex-snapshot
Data prefetching with co-operative caching
inferred← citeshttps://doi.org/10.1109/hpca.1995.386537openalex-snapshot
Access ordering and memory-conscious cache utilization
inferred← citeshttps://doi.org/10.1109/hpca.1995.386553openalex-snapshot
How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors?
inferred← citeshttps://doi.org/10.1109/hpca.1998.650569openalex-snapshot
Comparative evaluation of latency tolerance techniques for software distributed shared memory
inferred← citeshttps://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056020openalex-snapshot
Increasing multicore system efficiency through intelligent bandwidth shifting
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00061openalex-snapshot
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00040openalex-snapshot
Differential-Matching Prefetcher for Indirect Memory Access
inferred← citeshttps://doi.org/10.1109/ia3.2018.00009openalex-snapshot
Software Prefetching for Unstructured Mesh Applications
inferred← citeshttps://doi.org/10.1109/icapp.1996.562912openalex-snapshot
Reducing multithreaded frame cache miss ratio by prefetching and working frame set scheduling
inferred← citeshttps://doi.org/10.1109/iccad.2000.896510openalex-snapshot
MIST: an algorithm for memory miss traffic management
inferred← citeshttps://doi.org/10.1109/iccci.2014.6921756openalex-snapshot
Coalesced speculative prefetching and Interthread data dependences
inferred← citeshttps://doi.org/10.1109/iccct.2011.6075118openalex-snapshot
Realization of power aware software prefetching as a multi-objective optimization problem
inferred← citeshttps://doi.org/10.1109/iccd.1995.528797openalex-snapshot
A superscalar RISC processor with pseudo vector processing feature
inferred← citeshttps://doi.org/10.1109/iccd.1995.528916openalex-snapshot
Reducing data access penalty using intelligent opcode-driven cache prefetching
inferred← citeshttps://doi.org/10.1109/iccd.1998.727076openalex-snapshot
Evaluating the performance of active cache management schemes
inferred← citeshttps://doi.org/10.1109/iccd.2002.1106792openalex-snapshot
A framework for data prefetching using off-line training of Markovian predictors
inferred← citeshttps://doi.org/10.1109/iccd.2005.64openalex-snapshot
Hardware support for bulk data movement in server platforms
inferred← citeshttps://doi.org/10.1109/iccd.2018.00028openalex-snapshot
Array Tracking Prefetcher for Indirect Accesses
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00056openalex-snapshot
Static Function Prefetching for Efficient Code Management on Scratchpad Memory
inferred← citeshttps://doi.org/10.1109/iccd53106.2021.00059openalex-snapshot
HyperData: A Data Transfer Accelerator for Software Data Planes Based on Targeted Prefetching
inferred← citeshttps://doi.org/10.1109/iceac.2015.7352208openalex-snapshot
Machine learning techniques for improved data prefetching
inferred← citeshttps://doi.org/10.1109/icecc.2011.6067616openalex-snapshot
Dynamic block prefetching for tree search
inferred← citeshttps://doi.org/10.1109/iced.2008.4786750openalex-snapshot
Instruction prefetching using Basicblock prediction
inferred← citeshttps://doi.org/10.1109/icip.1996.560626openalex-snapshot
Prefetching scheme for image processing on shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/icme.2002.1035779openalex-snapshot
Memory performance optimizations for real-time software HDTV decoding
inferred← citeshttps://doi.org/10.1109/icpp.1994.57openalex-snapshot
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/icpp.1994.65openalex-snapshot
Cachier: A Tool for Automatically Inserting CICO Annotations
inferred← citeshttps://doi.org/10.1109/icpp.1994.71openalex-snapshot
Compiler Optimization Technique for Data Cache Prefetching Using a Small CAM Array
inferred← citeshttps://doi.org/10.1109/icpp.1994.81openalex-snapshot
Data Prefetching and Data Forwarding in Shared Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/icpp.1997.622660openalex-snapshot
An adaptive sequential prefetching scheme in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1109/icpp.1997.622661openalex-snapshot
Stride-directed prefetching for secondary caches
inferred← citeshttps://doi.org/10.1109/ipdps.2000.845983openalex-snapshot
Register assignment for software pipelining with partitioned register banks
inferred← citeshttps://doi.org/10.1109/ipdps.2003.1213178openalex-snapshot
Hierarchical clustered register file organization for VLIW processors
inferred← citeshttps://doi.org/10.1109/ipdps.2003.1213484openalex-snapshot
An executable analytical performance evaluation approach for early performance prediction
inferred← citeshttps://doi.org/10.1109/ipdps.2012.29openalex-snapshot
Competitive Cache Replacement Strategies for Shared Cache Environments
inferred← citeshttps://doi.org/10.1109/ipdps.2012.46openalex-snapshot
Optimizing Large-scale Graph Analysis on Multithreaded, Multicore Platforms
inferred← citeshttps://doi.org/10.1109/ipdpsw.2013.231openalex-snapshot
Compiler-Based Data Prefetching and Streaming Non-temporal Store Generation for the Intel(R) Xeon Phi(TM) Coprocessor
inferred← citeshttps://doi.org/10.1109/ipdpsw.2017.14openalex-snapshot
Redesigning OP2 Compiler to Use HPX Runtime Asynchronous Techniques
inferred← citeshttps://doi.org/10.1109/ipps.1993.262832openalex-snapshot
KSR1 multiprocessor: analysis of latency hiding techniques in a sparse solver
inferred← citeshttps://doi.org/10.1109/ipps.1994.288274openalex-snapshot
Can parallel algorithms enhance serial implementation?
inferred← citeshttps://doi.org/10.1109/ipps.1996.508052openalex-snapshot
A memory controller for improved performance of streamed computations on symmetric multiprocessors
inferred← citeshttps://doi.org/10.1109/ipps.1997.580946openalex-snapshot
Relative performance of hardware and software-only directory protocols under latency tolerating and reducing techniques
inferred← citeshttps://doi.org/10.1109/isca.1993.698568openalex-snapshot
Limitations Of Cache Prefetching On A Bus-based Multiprocessor
inferred← citeshttps://doi.org/10.1109/isca.1994.288164openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferred← citeshttps://doi.org/10.1109/isca.2003.1207016openalex-snapshot
Guided region prefetching: a cooperative hardware/software approach
inferred← citeshttps://doi.org/10.1109/isie.1994.333088openalex-snapshot
A concurrent hardware software management scheme for memory hierarchies
inferred← citeshttps://doi.org/10.1109/islped.2013.6629320openalex-snapshot
PreTrans: Reducing TLB CAM-search via page number prediction and speculative pre-translation
inferred← citeshttps://doi.org/10.1109/ispa/iucc.2017.00017openalex-snapshot
An Efficient Hardware Prefetcher Exploiting the Prefetch Potential of Long-Stride Access Pattern on Virtual Address
inferred← citeshttps://doi.org/10.1109/ispass.2006.1620801openalex-snapshot
Improved stride prefetching using extrinsic stream characteristics
inferred← citeshttps://doi.org/10.1109/ispass.2015.7095814openalex-snapshot
Performance and energy evaluation of data prefetching on intel Xeon Phi
inferred← citeshttps://doi.org/10.1109/ispass55109.2022.00002openalex-snapshot
Performance Analysis and Optimization with Little’s Law
inferred← citeshttps://doi.org/10.1109/isss.1996.565886openalex-snapshot
Memory organization for improved data cache performance in embedded processors
inferred← citeshttps://doi.org/10.1109/isuma.1995.527753openalex-snapshot
Fuzzy scheduling in compilers optimizations
inferred← citeshttps://doi.org/10.1109/l-ca.2004.3openalex-snapshot
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
inferred← citeshttps://doi.org/10.1109/mascot.2000.876582openalex-snapshot
Cache resident data locality analysis
inferred← citeshttps://doi.org/10.1109/mascots50786.2020.9285963openalex-snapshot
Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory
inferred← citeshttps://doi.org/10.1109/micro.1992.697003openalex-snapshot
An Efficient Architecture For Loop Based Data Preloading
inferred← citeshttps://doi.org/10.1109/micro.1993.282748openalex-snapshot
An evaluation of bottom-up and top-down thread generation techniques
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An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
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A limit study of local memory requirements using value reuse profiles
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SPAID: software prefetching in pointer- and call-intensive environments
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Cache miss heuristics and preloading techniques for general-purpose programs
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Exceeding the dataflow limit via value prediction
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A comparison of data prefetching on an access decoupled and superscalar machine
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Cache sensitive module scheduling
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Two-level hierarchical register file organization for VLIW processors
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Modulo scheduling with integrated register spilling for clustered VLIW architectures
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Stream Programming on General-Purpose Processors
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Optimizing software data prefetches with rotating registers
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Multi-chain prefetching: effective exploitation of inter-chain memory parallelism for pointer-chasing codes
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Data flow analysis for software prefetching linked data structures in Java
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Comparing and combining read miss clustering and software prefetching
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Transparent threads: resource sharing in SMT processors for high single-thread performance
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Architectural Support for the Stream Execution Model on General-Purpose Processors
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Page fault behavior and two prepaging schemes
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Dynamic and adaptive cache prefetch policies
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A dual-mode instruction prefetch scheme for improved worst case and average case program execution times
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Light-PREM: Automated software refactoring for predictable execution on COTS embedded systems
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A Highly Efficient SGEMM Implementation using DMA on the Intel/Movidius Myriad-2
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PASSION Runtime Library for parallel I/O
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Sunder: a programmable hardware prefetch architecture for numerical loops
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Tolerating late memory traps in dynamically scheduled processors
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Hardware Support for Accelerating Data Movement in Server Platform
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Acceleration of XML Parsing through Prefetching
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Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing
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Compiler driven data cache prefetching for high performance computers
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Analyzing In-Memory NoSQL Landscape
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A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck
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