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NUMA Aware Iterative Stencil Computations on Many-Core Systems

https://doi.org/10.1109/ipdps.2012.50
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/icpp.2011.47openalex-snapshot
Cache Accurate Time Skewing in Iterative Stencil Computations
inferredcites →https://doi.org/10.1109/ipdps.2000.845979openalex-snapshot
Using time skewing to eliminate idle time due to memory bandwidth and network limitations
inferredcites →https://doi.org/10.1109/ipdps.2007.370291openalex-snapshot
Towards Optimal Multi-level Tiling for Stencil Computations
inferredcites →https://doi.org/10.1109/ipdps.2010.5470421openalex-snapshot
An auto-tuning framework for parallel multicore stencil computations
inferredcites →https://doi.org/10.1109/ipdps.2011.70openalex-snapshot
PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures
inferredcites →https://doi.org/10.1109/ipdpsw.2010.5470813openalex-snapshot
Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory
inferredcites →https://doi.org/10.1109/sc.2008.5222004openalex-snapshot
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures
inferredcites →https://doi.org/10.1145/1111583.1111589openalex-snapshot
Impact of modern memory subsystems on cache optimizations for stencil computations
inferredcites →https://doi.org/10.1145/1148109.1148157openalex-snapshot
The cache complexity of multithreaded cache oblivious algorithms
inferredcites →https://doi.org/10.1145/1250734.1250761openalex-snapshot
Effective automatic parallelization of stencil computations
inferredcites →https://doi.org/10.1145/1273442.1250761openalex-snapshot
Effective automatic parallelization of stencil computations
inferredcites →https://doi.org/10.1145/1362622.1362691openalex-snapshot
Multi-level tiling
inferredcites →https://doi.org/10.1145/1375581.1375595openalex-snapshot
A practical automatic polyhedral parallelizer and locality optimizer
inferredcites →https://doi.org/10.1145/1379022.1375595openalex-snapshot
A practical automatic polyhedral parallelizer and locality optimizer
inferredcites →https://doi.org/10.1145/1772954.1772983openalex-snapshot
Parameterized tiling revisited
inferredcites →https://doi.org/10.1145/1810085.1810096openalex-snapshot
Cache oblivious parallelograms in iterative stencil computations
inferredcites →https://doi.org/10.1145/1810479.1810519openalex-snapshot
Low depth cache-oblivious algorithms
inferredcites →https://doi.org/10.1145/1989493.1989508openalex-snapshot
The pochoir stencil compiler
inferredcites →https://doi.org/10.5555/1413370.1413375openalex-snapshot
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-319-22786-3_36openalex-snapshot
A Graph-Based Locality-Aware Approach to Scalable Parallel Agent-Based Models of Spatial Interaction
inferred← citeshttps://doi.org/10.1007/978-3-319-52709-3_12openalex-snapshot
Automatically Optimizing Stencil Computations on Many-Core NUMA Architectures
inferred← citeshttps://doi.org/10.1007/978-3-319-75178-8_48openalex-snapshot
Data Partitioning Strategies for Stencil Computations on NUMA Systems
inferred← citeshttps://doi.org/10.1007/978-3-319-96983-1_42openalex-snapshot
NUMA Optimizations for Algorithmic Skeletons
inferred← citeshttps://doi.org/10.1007/978-981-10-6238-4_4openalex-snapshot
Work-Stealing for NUMA-enabled Architecture
inferred← citeshttps://doi.org/10.1109/hpcc-smartcity-dss.2016.0027openalex-snapshot
SAWS: Selective Asymmetry-Aware Work-Stealing for Asymmetric Multi-core Architectures
inferred← citeshttps://doi.org/10.1109/hpcc-smartcity-dss50907.2020.00015openalex-snapshot
Optimization and Performance Modeling of Stencil Computations on ARM Architectures
inferred← citeshttps://doi.org/10.1109/hpcsim.2014.6903695openalex-snapshot
An evaluation of the potential of flash SSD as large and slow memory for stencil computations
inferred← citeshttps://doi.org/10.1109/sbac-pad.2014.11openalex-snapshot
Accelerating Curvature Estimate in 3D Seismic Data Using GPGPU
inferred← citeshttps://doi.org/10.1109/sc41405.2020.00040openalex-snapshot
CAB-MPI: Exploring Interprocess Work-Stealing towards Balanced MPI Communication
inferred← citeshttps://doi.org/10.1109/tpds.2016.2615094openalex-snapshot
Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations
inferred← citeshttps://doi.org/10.1145/2597652.2597665openalex-snapshot
LAWS
inferred← citeshttps://doi.org/10.1145/2766450openalex-snapshot
Locality-Aware Work Stealing Based on Online Profiling and Auto-Tuning for Multisocket Multicore Architectures
inferred← citeshttps://doi.org/10.1145/3018743.3018744openalex-snapshot
Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils
inferred← citeshttps://doi.org/10.1145/3155284.3018744openalex-snapshot
Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils
inferred← citeshttps://doi.org/10.1145/3291058openalex-snapshot
Bandwidth and Locality Aware Task-stealing for Manycore Architectures with Bandwidth-Asymmetric Memory
inferred← citeshttps://doi.org/10.2172/1422949openalex-snapshot
Analytical Cost Metrics : Days of Future Past
inferred← citeshttps://doi.org/10.26599/tst.2019.9010036openalex-snapshot
PsmArena: Partitioned shared memory for NUMA-awareness in multithreaded scientific applications
inferred← citeshttps://doi.org/10.48550/arxiv.1902.07590openalex-snapshot
JArena: Partitioned Shared Memory for NUMA-awareness in Multi-threaded Scientific Applications
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