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PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Time Skewing for Parallel Computers
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Loop Transformation Recipes for Code Generation and Auto-Tuning
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Cache-Aware Multigrid Methods for Solving Poisson's Equation in Two Dimensions
inferredcites →https://doi.org/10.1007/s10766-010-0142-5openalex-snapshot
A Performance Study for Iterative Stencil Loops on GPUs with Ghost Zone Optimizations
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OSKI: A library of automatically tuned sparse matrix kernels
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A Simplex Method for Function Minimization
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Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization
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The OpenCL specification
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Parallel data-locality aware stencil computations on modern micro-architectures
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An auto-tuning framework for parallel multicore stencil computations
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The Design and Implementation of FFTW3
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SPIRAL: Code Generation for DSP Transforms
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Cetus: A Source-to-Source Compiler Infrastructure for Multicores
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Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
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Automatically Tuned Linear Algebra Software
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Tiling Optimizations for 3D Scientific Computations
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An efficient code generation technique for tiled iteration spaces
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Optimization and Performance Modeling of Stencil Computations on Modern Microprocessors
inferredcites →https://doi.org/10.1145/1034774.1034777openalex-snapshot
Automatic tiling of iterative stencil loops
inferredcites →https://doi.org/10.1145/1088149.1088197openalex-snapshot
Cache oblivious stencil computations
inferredcites →https://doi.org/10.1145/1250734.1250780openalex-snapshot
Parameterized tiled loops for free
inferredcites →https://doi.org/10.1145/1375581.1375595openalex-snapshot
A practical automatic polyhedral parallelizer and locality optimizer
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Risa/Asir---a computer algebra system
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3D finite difference computation on GPUs using CUDA
inferredcites →https://doi.org/10.1145/1810085.1810096openalex-snapshot
Cache oblivious parallelograms in iterative stencil computations
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Analysis of Tissue and Arterial Blood Temperatures in the Resting Human Forearm
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Analysis of Tissue and Arterial Blood Temperatures in the Resting Human Forearm
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Cache-Efficient Multigrid Algorithms
inferredcites →https://doi.org/10.1201/b10376openalex-snapshot
Scientific Computing with Multicore and Accelerators
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Mixed-Precision GPU-Multigrid Solvers with Strong Smoothers
inferredcites →https://doi.org/10.1201/b10376-26openalex-snapshot
Manycore Stencil Computations in Hyperthermia Applica- tions
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Automatically Tuned Linear Algebra Software
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Towards Domain-Specific Computing for Stencil Codes in HPC
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Zero-Overhead Interfaces for High-Performance Computing Libraries and Kernels
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AlphaSparse: Generating High Performance SpMV Codes Directly from Sparse Matrices
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Automated Code Generation of High-Order Stencils for a Dataflow Architecture
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A Performance-Portable MultiGPU Implementation of 3D Euler Equations using ProtoX and IRIS
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mARGOt: A Dynamic Autotuning Framework for Self-Aware Approximate Computing
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Efficient Hardware Design of Iterative Stencil Loops
inferred← citeshttps://doi.org/10.1109/tcc.2017.2710311openalex-snapshot
Fault Tolerant Stencil Computation on Cloud-Based GPU Spot Instances
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Autogeneration and Autotuning of 3D Stencil Codes on Homogeneous and Heterogeneous GPU Clusters
inferred← citeshttps://doi.org/10.1109/tpds.2016.2615094openalex-snapshot
Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations
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Accelerating Atmospheric Chemical Kinetics for Climate Simulations
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Level-Based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication
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Pegasus: Performance Engineering for Software Applications Targeting HPC Systems
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Autotuning Wavefront Abstractions for Heterogeneous Architectures
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ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers
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Target-Specific Refinement of Multigrid Codes
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The OPS Domain Specific Abstraction for Multi-block Structured Grid Computations
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Devito: Automated Fast Finite Difference Computation
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Modeling the Performance of Geometric Multigrid Stencils on Multicore Computer Architectures
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Multicore-Optimized Wavefront Diamond Blocking for Optimizing Stencil Updates
inferred← citeshttps://doi.org/10.1142/s0129626412400051openalex-snapshot
AUTO-TUNING PARALLEL SKELETONS
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The Relation Between Diamond Tiling and Hexagonal Tiling
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Code Refinement of Stencil Codes
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High-Level Programming of Stencil Computations on Multi-GPU Systems Using the SkelCL Library
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Auto-generation and auto-tuning of 3D stencil codes on GPU clusters
inferred← citeshttps://doi.org/10.1145/2304576.2304619openalex-snapshot
High-performance code generation for stencil computations on GPU architectures
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A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices
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A stencil compiler for short-vector SIMD architectures
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A scalable, efficient scheme for evaluation of stencil computations over unstructured meshes
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Hybrid Hexagonal/Classical Tiling for GPUs
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On Expressing Strategies for Directive-Driven Multicore Programing Models
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Autotuning Wavefront Applications for Multicore Multi-GPU Hybrid Architectures
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Autotuning Wavefront Applications for Multicore Multi-GPU Hybrid Architectures
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Hybrid Hexagonal/Classical Tiling for GPUs
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Converting Stencils to Accumulations Forcommunication-Avoiding Optimizationin Geometric Multigrid
inferred← citeshttps://doi.org/10.1145/2716282.2716290openalex-snapshot
Forma: a DSL for image processing applications to target GPUs and multi-core CPUs
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Meta-programming and auto-tuning in the search for high performance GPU code
inferred← citeshttps://doi.org/10.1145/2830018.2830020openalex-snapshot
From DSL to HPC component-based runtime
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On How to Accelerate Iterative Stencil Loops
inferred← citeshttps://doi.org/10.1145/2872362.2872411openalex-snapshot
Architecture-Adaptive Code Variant Tuning
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Effective resource management for enhancing performance of 2D and 3D stencils on GPUs
inferred← citeshttps://doi.org/10.1145/2908080.2908117openalex-snapshot
Verified lifting of stencil computations
inferred← citeshttps://doi.org/10.1145/2925426.2926286openalex-snapshot
Polly-ACC Transparent compilation to heterogeneous hardware
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Architecture-Adaptive Code Variant Tuning
inferred← citeshttps://doi.org/10.1145/2954680.2872411openalex-snapshot
Architecture-Adaptive Code Variant Tuning
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Resource Conscious Reuse-Driven Tiling for GPUs
inferred← citeshttps://doi.org/10.1145/2980024.2872411openalex-snapshot
Architecture-Adaptive Code Variant Tuning
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Verified lifting of stencil computations
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Program autotuning as a service
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Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils
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LARA as a language-independent aspect-oriented programming approach
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A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model
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