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A Theoretical Framework for Algorithm-Architecture Co-design

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-52048-1_52openalex-snapshot
Energy-time trade-offs in VLSI computations
inferredcites →https://doi.org/10.1007/978-3-540-69338-3_14openalex-snapshot
Performance/Energy Optimization of DSP Transforms on the XScale Processor
inferredcites →https://doi.org/10.1007/978-3-642-19328-6_1openalex-snapshot
Exascale Computing Technology Challenges
inferredcites →https://doi.org/10.1007/978-3-642-23397-5_10openalex-snapshot
Communication-Optimal Parallel 2.5D Matrix Multiplication and LU Factorization Algorithms
inferredcites →https://doi.org/10.1016/0096-3003(90)90108-fopenalex-snapshot
On the multigrid F-cycle
inferredcites →https://doi.org/10.1016/j.parco.2010.11.003openalex-snapshot
Self-similarity of parallel machines
inferredcites →https://doi.org/10.1016/s0020-0190(00)00214-3openalex-snapshot
Towards an energy complexity of computation
inferredcites →https://doi.org/10.1109/2.917539openalex-snapshot
Power: a first-class architectural design constraint
inferredcites →https://doi.org/10.1109/clustr.2008.4663777openalex-snapshot
Prediction of behavior of MPI applications
inferredcites →https://doi.org/10.1109/clustr.2008.4663799openalex-snapshot
SPRAT: Runtime processor selection for energy-aware computing
inferredcites →https://doi.org/10.1109/date.2009.5090700openalex-snapshot
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
inferredcites →https://doi.org/10.1109/icpp.2009.74openalex-snapshot
Analysis of Parallel Algorithms for Energy Conservation in Scalable Multicore Architectures
inferredcites →https://doi.org/10.1109/ipdps.2010.5470354openalex-snapshot
Oblivious algorithms for multicores and network of processors
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/jproc.2004.840301openalex-snapshot
The Design and Implementation of FFTW3
inferredcites →https://doi.org/10.1109/mc.2008.209openalex-snapshot
Amdahl's Law in the Multicore Era
inferredcites →https://doi.org/10.1109/mc.2008.224openalex-snapshot
Efficient Embedded Computing
inferredcites →https://doi.org/10.1109/mc.2008.494openalex-snapshot
Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era
inferredcites →https://doi.org/10.1109/micro.2010.36openalex-snapshot
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
inferredcites →https://doi.org/10.1109/micro.2010.42openalex-snapshot
Understanding the Energy Consumption of Dynamic Random Access Memories
inferredcites →https://doi.org/10.1109/mm.2011.48openalex-snapshot
Simulating Whole Supercomputer Applications
inferredcites →https://doi.org/10.1109/mm.2011.58openalex-snapshot
Simulating Whole Supercomputer Applications
inferredcites →https://doi.org/10.1109/mm.2011.77openalex-snapshot
Toward Dark Silicon in Servers
inferredcites →https://doi.org/10.1109/mm.2011.89openalex-snapshot
GPUs and the Future of Parallel Computing
inferredcites →https://doi.org/10.1109/mm.2012.17openalex-snapshot
Dark Silicon and the End of Multicore Scaling
inferredcites →https://doi.org/10.1109/sffcs.1999.814600openalex-snapshot
Cache-oblivious algorithms
inferredcites →https://doi.org/10.1109/wwc.2001.16openalex-snapshot
Modeling application performance by convolving machine signatures with application profiles
inferredcites →https://doi.org/10.1109/wwc.2001.990754openalex-snapshot
Modeling application performance by convolving machine signatures with application profiles
inferredcites →https://doi.org/10.1137/1.9781611970999openalex-snapshot
Computational Frameworks for the Fast Fourier Transform
inferredcites →https://doi.org/10.1137/1.9781611971446openalex-snapshot
Applied Numerical Linear Algebra
inferredcites →https://doi.org/10.1137/s0895479896297744openalex-snapshot
Locality of Reference in LU Decomposition with Partial Pivoting
inferredcites →https://doi.org/10.1145/1188455.1188534openalex-snapshot
Architecture---A performance comparison through benchmarking and modeling of three leading supercomputers
inferredcites →https://doi.org/10.1145/155332.155333openalex-snapshot
LogP: towards a realistic model of parallel computation
inferredcites →https://doi.org/10.1145/1669112.1669172openalex-snapshot
McPAT
inferredcites →https://doi.org/10.1145/173284.155333openalex-snapshot
LogP: towards a realistic model of parallel computation
inferredcites →https://doi.org/10.1145/1810479.1810519openalex-snapshot
Low depth cache-oblivious algorithms
inferredcites →https://doi.org/10.1145/1851476.1851564openalex-snapshot
LogGOPSim
inferredcites →https://doi.org/10.1145/1941487.1941507openalex-snapshot
The future of microprocessors
inferredcites →https://doi.org/10.1145/1964218.1964223openalex-snapshot
Performance analysis of a hybrid MPI/CUDA implementation of the NASLU benchmark
inferredcites →https://doi.org/10.1145/1964218.1964225openalex-snapshot
The structural simulation toolkit
inferredcites →https://doi.org/10.1145/1995896.1995924openalex-snapshot
Modeling the performance of an algebraic multigrid cycle on HPC platforms
inferredcites →https://doi.org/10.1145/2000064.2000108openalex-snapshot
Dark silicon and the end of multicore scaling
inferredcites →https://doi.org/10.1145/2063384.2063421openalex-snapshot
Using the TOP500 to trace and project technology and architecture trends
inferredcites →https://doi.org/10.1145/2063384.2063440openalex-snapshot
An early performance analysis of POWER7-IH HPC systems
inferredcites →https://doi.org/10.1145/227234.227246openalex-snapshot
Programming parallel algorithms
inferredcites →https://doi.org/10.1145/2304576.2304604openalex-snapshot
On the communication complexity of 3D FFTs and its implications for Exascale
inferredcites →https://doi.org/10.1145/339647.339657openalex-snapshot
Wattch
inferredcites →https://doi.org/10.1145/62212.62230openalex-snapshot
Energy consumption in VLSI circuits
inferredcites →https://doi.org/10.1145/800076.802486openalex-snapshot
I/O complexity
inferredcites →https://doi.org/10.1177/1094342010387806openalex-snapshot
Trace-based performance analysis for the petascale simulation code FLASH
inferredcites →https://doi.org/10.1190/1.3284053openalex-snapshot
Selecting the right hardware for reverse time migration
inferredcites →https://doi.org/10.5860/choice.35-3919openalex-snapshot
Applied numerical linear algebra

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-319-05215-1_5openalex-snapshot
Analyzing the Energy and Power Consumption of Remote Memory Accesses in the OpenSHMEM Model
inferred← citeshttps://doi.org/10.1007/978-3-319-10214-6_9openalex-snapshot
SESH Framework: A Space Exploration Framework for GPU Application and Hardware Codesign
inferred← citeshttps://doi.org/10.1007/s10845-015-1170-1openalex-snapshot
Evolutionary fuzzy intelligent system for multi-objective supply chain network designs: an agent-based optimization state of the art
inferred← citeshttps://doi.org/10.1007/s11554-016-0563-5openalex-snapshot
A multi-FPGA architecture-based real-time TFM ultrasound imaging
inferred← citeshttps://doi.org/10.1057/s41273-016-0036-7openalex-snapshot
Energy consumption of synchronization algorithms in distributed simulations
inferred← citeshttps://doi.org/10.1109/ds-rt.2015.32openalex-snapshot
An Empirical Study of Energy Consumption in Distributed Simulations
inferred← citeshttps://doi.org/10.1109/iiswc.2014.6983061openalex-snapshot
Extending the roofline model: Bottleneck analysis with microarchitectural constraints
inferred← citeshttps://doi.org/10.1109/ipdps.2015.71openalex-snapshot
An Approach for Energy Efficient Execution of Hybrid Parallel Programs
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.206openalex-snapshot
Analyzing the Energy Efficiency of the Fast Multipole Method Using a DVFS-Aware Energy Model
inferred← citeshttps://doi.org/10.1109/mascots.2016.54openalex-snapshot
Modeling the Energy-Time Performance of MIC Architecture System
inferred← citeshttps://doi.org/10.1109/sc.2018.00036openalex-snapshot
Siena: Exploring the Design Space of Heterogeneous Memory Systems
inferred← citeshttps://doi.org/10.1145/2534645.2534654openalex-snapshot
A framework for an in-depth comparison of scale-up and scale-out
inferred← citeshttps://doi.org/10.1145/2576779.2576787openalex-snapshot
A CPU
inferred← citeshttps://doi.org/10.1145/2588768.2576787openalex-snapshot
A CPU
inferred← citeshttps://doi.org/10.1145/2612669.2612694openalex-snapshot
On characterizing the data movement complexity of computational DAGs for parallel execution
inferred← citeshttps://doi.org/10.1145/2744769.2744888openalex-snapshot
Parallel circuit simulation using the direct method on a heterogeneous cloud
inferred← citeshttps://doi.org/10.1145/2769458.2773791openalex-snapshot
On Energy Consumption in Distributed Simulations
inferred← citeshttps://doi.org/10.1145/2866577openalex-snapshot
Research Challenges in Parallel and Distributed Simulation
inferred← citeshttps://doi.org/10.1145/2901378.2901395openalex-snapshot
Profiling Energy Consumption in Distributed Simulations
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