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Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-61730-2_13openalex-snapshot
RaPiD — Reconfigurable pipelined datapath
inferredcites →https://doi.org/10.1007/s10766-006-0028-8openalex-snapshot
Amdahl’s Law Revisited for Single Chip Systems
inferredcites →https://doi.org/10.1016/0167-8191(95)00071-2openalex-snapshot
Heterogeneous computing machines and Amdahl's law
inferredcites →https://doi.org/10.1109/2.917539openalex-snapshot
Power: a first-class architectural design constraint
inferredcites →https://doi.org/10.1109/fccm.2009.14openalex-snapshot
Accelerating SPICE Model-Evaluation using FPGAs
inferredcites →https://doi.org/10.1109/fpga.1997.624600openalex-snapshot
Garp: a MIPS processor with a reconfigurable coprocessor
inferredcites →https://doi.org/10.1109/hpca.2009.4798263openalex-snapshot
Reconciling specialization and flexibility through compound circuits
inferredcites →https://doi.org/10.1109/iedm.2005.1609253openalex-snapshot
Scaling, power, and the future of CMOS
inferredcites →https://doi.org/10.1109/isca.1999.765937openalex-snapshot
PipeRench: a coprocessor for streaming multimedia acceleration
inferredcites →https://doi.org/10.1109/isca.2000.854393openalex-snapshot
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
inferredcites →https://doi.org/10.1109/jproc.2004.840306openalex-snapshot
SPIRAL: Code Generation for DSP Transforms
inferredcites →https://doi.org/10.1109/l-ca.2006.6openalex-snapshot
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors
inferredcites →https://doi.org/10.1109/mc.2005.379openalex-snapshot
Heterogeneous chip multiprocessors
inferredcites →https://doi.org/10.1109/mc.2008.209openalex-snapshot
Amdahl's Law in the Multicore Era
inferredcites →https://doi.org/10.1109/mc.2008.494openalex-snapshot
Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era
inferredcites →https://doi.org/10.1109/micro.2005.33openalex-snapshot
The Cell Processor Architecture
inferredcites →https://doi.org/10.1109/mm.2003.1196116openalex-snapshot
The AMD opteron processor for multiprocessor servers
inferredcites →https://doi.org/10.1109/mm.2007.4378780openalex-snapshot
On-Chip Interconnection Architecture of the Tile Processor
inferredcites →https://doi.org/10.1109/mm.2010.38openalex-snapshot
Power7: IBM's Next-Generation Server Processor
inferredcites →https://doi.org/10.1109/mm.2010.7openalex-snapshot
Accelerating Critical Section Execution with Asymmetric Multicore Architectures
inferredcites →https://doi.org/10.1109/pact.2005.42openalex-snapshot
Maximizing CMP throughput with mediocre cores
inferredcites →https://doi.org/10.1109/sasp.2008.4570793openalex-snapshot
Accelerating Compute-Intensive Applications with GPUs and FPGAs
inferredcites →https://doi.org/10.1109/tpds.2009.41openalex-snapshot
On the Interplay of Parallelization, Program Performance, and Energy Consumption
inferredcites →https://doi.org/10.1109/vlsid.2007.140openalex-snapshot
Scaling, Power and the Future of CMOS
inferredcites →https://doi.org/10.1145/1028176.1006734openalex-snapshot
Evaluating the Imagine Stream Architecture
inferredcites →https://doi.org/10.1145/1117201.1117205openalex-snapshot
Measuring the gap between FPGAs and ASICs
inferredcites →https://doi.org/10.1145/1391469.1391572openalex-snapshot
Formal datapath representation and manipulation for implementing DSP transforms
inferredcites →https://doi.org/10.1145/1465482.1465560openalex-snapshot
Validity of the single processor approach to achieving large scale computing capabilities
inferredcites →https://doi.org/10.1145/1508128.1508139openalex-snapshot
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation
inferredcites →https://doi.org/10.1145/1555754.1555804openalex-snapshot
Performance and power of cache-based reconfigurable computing
inferredcites →https://doi.org/10.1145/1815961.1816011openalex-snapshot
Modeling critical sections in Amdahl's law and its implications for multicore design
inferredcites →https://doi.org/10.1145/1815961.1816021openalex-snapshot
Debunking the 100X GPU vs. CPU myth
inferredcites →https://doi.org/10.1145/192724.192749openalex-snapshot
A high-performance microarchitecture with hardware-programmable functional units
inferredcites →https://doi.org/10.1145/300979.300982openalex-snapshot
PipeRench: a co/processor for streaming multimedia acceleration
inferredcites →https://doi.org/10.1145/339647.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1535/itj.1103.03openalex-snapshot
Package Technology to Address the Memory Bandwidth Challenge for Terascale Computing
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Challenges in Computing for Nanoscale Technologies
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Towards Breaking the Memory Bandwidth Wall Using Approximate Value Prediction
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Cooperative Computing Techniques for a Deeply Fused and Heterogeneous Many-Core Processor Architecture
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Lyra: password-based key derivation with tunable memory and processing costs
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Energy aware computer vision algorithm deployment on heterogeneous architectures
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The need for heterogeneous network-on-chip architectures with GPGPUs
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Dark Silicon and the History of Computing
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Energy aware edge computing: A survey
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Voltage island based heterogeneous NoC design through constraint programming
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A survey of memory architecture for 3D chip multi-processors
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The effect of communication and synchronization on Amdahl’s law in multicore systems
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Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors
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Amdahl's law in the context of heterogeneous many‐core systems – a survey
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SneakySnake: a fast and accurate universal genome pre-alignment filter for CPUs, GPUs and FPGAs
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Application-Specific Heterogeneous Network-on-Chip Design
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Optimal Task Scheduling for Distributed Cluster With Active Storage Devices and Accelerated Nodes
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Transforming a linear algebra core to an FFT accelerator
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Understanding the design space of DRAM-optimized hardware FFT accelerators
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Heterogeneous architecture design with emerging 3D and non-volatile memory technologies
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PyTPU: Migration of Python Code for Heterogenous Acceleration with Automated Test Generation
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On-the-fly energy minimization for multi-mode real-time systems on heterogeneous platforms
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GPGPU for industrial control systems
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Hard Real-Time Capable OPC UA Server as Hardware Peripheral for Single Chip IoT Systems
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High level programming framework for FPGAs in the data center
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Automated Design of FPGAs Facilitated by Cycle-Free Routing
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Telescoping Architectures: Evaluating Next-Generation Heterogeneous Computing
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Dark silicon and the end of multicore scaling
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A defect-tolerant accelerator for emerging high-performance applications
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Power challenges may end the multicore era
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Explicit Java control of low-power heterogeneous parallel processing in the ToucHMore project
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On heterogeneous network-on-chip design based on constraint programming
inferred← citeshttps://doi.org/10.1145/2636342openalex-snapshot
A Survey of Methods for Analyzing and Improving GPU Energy Efficiency
inferred← citeshttps://doi.org/10.1145/2678373.2665743openalex-snapshot
Improving the energy efficiency of big cores
inferred← citeshttps://doi.org/10.1145/2684746.2689136openalex-snapshot
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only)
inferred← citeshttps://doi.org/10.1145/2716282.2716291openalex-snapshot
Efficient utilization of GPGPU cache hierarchy
inferred← citeshttps://doi.org/10.1145/2742854.2742860openalex-snapshot
Scaling application properties to exascale
inferred← citeshttps://doi.org/10.1145/2744769.2744781openalex-snapshot
A reconfigurable analog substrate for highly efficient maximum flow computation
inferred← citeshttps://doi.org/10.1145/2786572.2788711openalex-snapshot
Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism
inferred← citeshttps://doi.org/10.1145/2845084openalex-snapshot
Resistive GP-SIMD Processing-In-Memory
inferred← citeshttps://doi.org/10.1145/2872362.2872412openalex-snapshot
Analyzing Behavior Specialized Acceleration
inferred← citeshttps://doi.org/10.1145/2934583.2934637openalex-snapshot
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency
inferred← citeshttps://doi.org/10.1145/2947357.2947361openalex-snapshot
A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip
inferred← citeshttps://doi.org/10.1145/2948976openalex-snapshot
Implementing Dense Optical Flow Computation on a Heterogeneous FPGA SoC in C
inferred← citeshttps://doi.org/10.1145/2968455.2968509openalex-snapshot
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip
inferred← citeshttps://doi.org/10.1145/3030207.3030244openalex-snapshot
Collaborative Computing for Heterogeneous Integrated Systems
inferred← citeshttps://doi.org/10.1145/3123939.3124541openalex-snapshot
Estimating and understanding architectural risk
inferred← citeshttps://doi.org/10.1145/3241050openalex-snapshot
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems
inferred← citeshttps://doi.org/10.1145/3360047openalex-snapshot
Language Support for Navigating Architecture Design in Closed Form
inferred← citeshttps://doi.org/10.1145/3427377openalex-snapshot
Bayesian Optimization for Efficient Accelerator Synthesis
inferred← citeshttps://doi.org/10.1145/3431920.3439294openalex-snapshot
PRGA: An Open-Source FPGA Research and Prototyping Framework
inferred← citeshttps://doi.org/10.1145/3446382.3448360openalex-snapshot
The Role of Edge Offload for Hardware-Accelerated Mobile Devices
inferred← citeshttps://doi.org/10.1145/3468264.3468610openalex-snapshot
HeteroFuzz: fuzz testing to detect platform dependent divergence for heterogeneous applications
inferred← citeshttps://doi.org/10.1145/3486880.3486882openalex-snapshot
The Role of Edge Offload for Hardware - Accelerated Mobile Devices
inferred← citeshttps://doi.org/10.1145/3544974openalex-snapshot
A Survey on Memory-centric Computer Architectures
inferred← citeshttps://doi.org/10.1145/3767110.3767114openalex-snapshot
Memory Sandbox 2.0: A Framework for Enabling HBM2e vs HBM2 Performance and Telemetry Analysis on Xilinx FPGAs
inferred← citeshttps://doi.org/10.1145/3769102.3770616openalex-snapshot
Does Accurate Real-Time AI Need Edge Offload?
inferred← citeshttps://doi.org/10.1155/2012/450302openalex-snapshot
Homogeneous and Heterogeneous MPSoC Architectures with Network‐On‐Chip Connectivity for Low‐Power and Real‐Time Multimedia Signal Processing
inferred← citeshttps://doi.org/10.11606/d.3.2016.tde-29062016-085500openalex-snapshot
Lyra: uma função de derivação de chaves com custos de memória e processamento configuráveis.
inferred← citeshttps://doi.org/10.11606/t.3.2016.tde-26082016-150620openalex-snapshot
Lyra2: password hashing scheme with improved security against time-memory trade-offs.
inferred← citeshttps://doi.org/10.1184/r1/6469421openalex-snapshot
The Main Memory System: Challenges and Opportunities
inferred← citeshttps://doi.org/10.1186/s13639-016-0037-7openalex-snapshot
A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection
inferred← citeshttps://doi.org/10.14529/jsfi140302openalex-snapshot
Research Problems and Opportunities in Memory Systems
inferred← citeshttps://doi.org/10.1504/ijhpcn.2017.10005140openalex-snapshot
pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing
inferred← citeshttps://doi.org/10.1504/ijhpsa.2014.061466openalex-snapshot
Amdahl's and Hill-Marty laws revisited for FPGA-based MPSoCs: from theory to practice
inferred← citeshttps://doi.org/10.15781/t2t727x53openalex-snapshot
Light curve fitting on heterogeneous computers
inferred← citeshttps://doi.org/10.1587/transinf.2017rcp0011openalex-snapshot
FPGA Components for Integrating FPGAs into Robot Systems
inferred← citeshttps://doi.org/10.1587/transinf.2018rcp0004openalex-snapshot
Automatic Generation Tool of FPGA Components for Robots
inferred← citeshttps://doi.org/10.17559/tv-20171107024958openalex-snapshot
Application of Laser Sensor in Urban Vehicle Type Detection
inferred← citeshttps://doi.org/10.17918/etd-6374openalex-snapshot
Instrumenting and analyzing platform-independent communication in applications
inferred← citeshttps://doi.org/10.18130/v3sw1sopenalex-snapshot
First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems
inferred← citeshttps://doi.org/10.19070/2332-287x-1400015openalex-snapshot
Suicide Cases in Manipal, South India: An Autopsy Study
inferred← citeshttps://doi.org/10.2197/ipsjtsldm.8.51openalex-snapshot
Heterogeneous Multi-core Architectures
inferred← citeshttps://doi.org/10.31274/etd-180810-2925openalex-snapshot
Addressing the feasibility of USI-based threads scheduler on polymorphic computing system
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