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Compiler-Directed Transformation for Higher-Order Stencils
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/nla.1808openalex-snapshot
Improving the arithmetic intensity of multigrid with the help of polynomial smoothers
inferredcites →https://doi.org/10.1007/978-3-642-13374-9_4openalex-snapshot
Loop Transformation Recipes for Code Generation and Auto-Tuning
inferredcites →https://doi.org/10.1007/978-3-642-14390-8_52openalex-snapshot
Introducing the Semi-stencil Algorithm
inferredcites →https://doi.org/10.1007/978-3-642-19861-8_13openalex-snapshot
Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures
inferredcites →https://doi.org/10.1007/978-3-642-88434-4openalex-snapshot
The Numerical Treatment of Differential Equations
inferredcites →https://doi.org/10.1007/978-3-662-05500-7openalex-snapshot
The Numerical Treatment of Differential Equations
inferredcites →https://doi.org/10.1109/compsac.2009.82openalex-snapshot
Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization
inferredcites →https://doi.org/10.1109/hipc.2013.6799131openalex-snapshot
Compiler generation and autotuning of communication-avoiding operators for geometric multigrid
inferredcites →https://doi.org/10.1109/ipdps.2000.845979openalex-snapshot
Using time skewing to eliminate idle time due to memory bandwidth and network limitations
inferredcites →https://doi.org/10.1109/ipdps.2008.4536295openalex-snapshot
Lattice Boltzmann simulation optimization on leading multicore platforms
inferredcites →https://doi.org/10.1109/ipdps.2011.70openalex-snapshot
PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures
inferredcites →https://doi.org/10.1109/sc.2000.10015openalex-snapshot
Tiling Optimizations for 3D Scientific Computations
inferredcites →https://doi.org/10.1109/sc.2008.5222004openalex-snapshot
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures
inferredcites →https://doi.org/10.1109/sc.2010.2openalex-snapshot
3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs
inferredcites →https://doi.org/10.1109/sc.2012.85openalex-snapshot
Optimization of geometric multigrid for emerging multi- and manycore processors
inferredcites →https://doi.org/10.1137/070693199openalex-snapshot
Optimization and Performance Modeling of Stencil Computations on Modern Microprocessors
inferredcites →https://doi.org/10.1137/110820105openalex-snapshot
A Fourth-Order Accurate Finite-Volume Method with Structured Adaptive Mesh Refinement for Solving the Advection-Diffusion Equation
inferredcites →https://doi.org/10.1145/1048935.1050213openalex-snapshot
Evaluation of Cache-based Superscalar and Cacheless Vector Architectures for Scientific Computations
inferredcites →https://doi.org/10.1145/1128022.1128027openalex-snapshot
The potential of the cell processor for scientific computing
inferredcites →https://doi.org/10.1145/1250734.1250761openalex-snapshot
Effective automatic parallelization of stencil computations
inferredcites →https://doi.org/10.1145/1513895.1513905openalex-snapshot
3D finite difference computation on GPUs using CUDA
inferredcites →https://doi.org/10.1145/2063384.2063458openalex-snapshot
Extracting ultra-scale Lattice Boltzmann performance via hierarchical and distributed auto-tuning
inferredcites →https://doi.org/10.1145/2259016.2259037openalex-snapshot
Auto-generation and auto-tuning of 3D stencil codes on GPU clusters
inferredcites →https://doi.org/10.1145/2259016.2259044openalex-snapshot
Hierarchical overlapped tiling
inferredcites →https://doi.org/10.1145/2304576.2304619openalex-snapshot
High-performance code generation for stencil computations on GPU architectures
inferredcites →https://doi.org/10.1145/2435264.2435273openalex-snapshot
Polyhedral-based data reuse optimization for configurable computing
inferredcites →https://doi.org/10.1145/2594291.2594342openalex-snapshot
A framework for enhancing data reuse via associative reordering
inferredcites →https://doi.org/10.1145/2666356.2594342openalex-snapshot
A framework for enhancing data reuse via associative reordering
inferredcites →https://doi.org/10.1145/2686745.2686749openalex-snapshot
Converting Stencils to Accumulations Forcommunication-Avoiding Optimizationin Geometric Multigrid
inferredcites →https://doi.org/10.1145/301618.301668openalex-snapshot
New tiling techniques to improve cache temporal locality
inferredcites →https://doi.org/10.1145/377792.377807openalex-snapshot
Eliminating redundancies in sum-of-product array computations
inferredcites →https://doi.org/10.1177/1094342004041295openalex-snapshot
Cache-Efficient Multigrid Algorithms
inferredcites →https://doi.org/10.1504/pcfd.2008.018088openalex-snapshot
Introducing a parallel cache oblivious blocking approach for the lattice Boltzmann method
inferredcites →https://doi.org/10.5555/1413370.1413375openalex-snapshot
Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures
inferredcites →https://doi.org/10.5555/2388996.2389126openalex-snapshot
Optimization of geometric multigrid for emerging multi- and manycore processors
inferredcites →https://doi.org/10.7282/t3zg6wvvopenalex-snapshot
Time Skewing: A Value-Based Approach to Optimizing for Memory Locality
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-72789-5_10openalex-snapshot
A Structured Grid Solver with Polyhedral+Dataflow Representation
inferred← citeshttps://doi.org/10.1007/s11390-016-1696-5openalex-snapshot
Highly Optimized Code Generation for Stencil Codes with Computation Reuse for GPUs
inferred← citeshttps://doi.org/10.1016/j.parco.2017.04.002openalex-snapshot
Compiler-based code generation and autotuning for geometric multigrid on GPU-accelerated supercomputers
inferred← citeshttps://doi.org/10.1016/j.procs.2016.05.293openalex-snapshot
Performance Analysis and Optimization of a Hybrid Seismic Imaging Application
inferred← citeshttps://doi.org/10.1109/icpads.2016.0137openalex-snapshot
Evaluation of Flash-Based Out-of-Core Stencil Computation Algorithms for SSD-Equipped Clusters
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00085openalex-snapshot
Roofline Guided Design and Analysis of a Multi-stencil CFD Solver for Multicore Performance
inferred← citeshttps://doi.org/10.1109/ipdps53621.2022.00069openalex-snapshot
An Efficient Vectorization Scheme for Stencil Computation
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.48openalex-snapshot
Blk-Tune: Blocking Parameter Auto-Tuning to Minimize Input-Output Traffic for Flash-Based Out-of-Core Stencil Computations
inferred← citeshttps://doi.org/10.1109/ipdpsw.2017.152openalex-snapshot
Automating Compiler-Directed Autotuning for Phased Performance Behavior
inferred← citeshttps://doi.org/10.1109/p3hpc.2018.00009openalex-snapshot
Delivering Performance-Portable Stencil Computations on CPUs and GPUs Using Bricks
inferred← citeshttps://doi.org/10.1109/sbac-pad.2016.18openalex-snapshot
Speeding Up Stencil Computations with Kernel Convolution
inferred← citeshttps://doi.org/10.1109/sc.2018.00049openalex-snapshot
Associative Instruction Reordering to Alleviate Register Pressure
inferred← citeshttps://doi.org/10.1109/sc41405.2020.00089openalex-snapshot
Pencil: A Pipelined Algorithm for Distributed Stencils
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00059openalex-snapshot
LoRAStencil: Low-Rank Adaptation of Stencil Computation on Tensor Cores
inferred← citeshttps://doi.org/10.1109/scw63240.2024.00159openalex-snapshot
High-Performance, Scalable Geometric Multigrid via Fine-Grain Data Blocking for GPUs
inferred← citeshttps://doi.org/10.1109/tpds.2025.3650515openalex-snapshot
SMEStencil: Optimizing High-Order Stencils on ARM Multicore Using SME Unit
inferred← citeshttps://doi.org/10.1145/3126908.3126968openalex-snapshot
Optimizing geometric multigrid method computation using a DSL approach
inferred← citeshttps://doi.org/10.1145/3178487.3178500openalex-snapshot
Register optimizations for stencils on GPUs
inferred← citeshttps://doi.org/10.1145/3178487.3178537openalex-snapshot
SIMD code generation for stencils on brick decompositions
inferred← citeshttps://doi.org/10.1145/3200691.3178500openalex-snapshot
Register optimizations for stencils on GPUs
inferred← citeshttps://doi.org/10.1145/3200691.3178537openalex-snapshot
SIMD code generation for stencils on brick decompositions
inferred← citeshttps://doi.org/10.1145/3209208openalex-snapshot
Extreme-Scale High-Order WENO Simulations of 3-D Detonation Wave with 10 Million Cores
inferred← citeshttps://doi.org/10.1145/3295500.3356162openalex-snapshot
A versatile software systolic execution model for GPU memory-bound kernels
inferred← citeshttps://doi.org/10.1145/3295500.3356210openalex-snapshot
Exploiting reuse and vectorization in blocked stencil computations on CPUs and GPUs
inferred← citeshttps://doi.org/10.1145/3337821.3337848openalex-snapshot
Cartesian Collective Communication
inferred← citeshttps://doi.org/10.1145/3458817.3476154openalex-snapshot
Reducing redundancy in data organization and arithmetic calculation for stencil computations
inferred← citeshttps://doi.org/10.1145/3624062.3624177openalex-snapshot
Performance Portability Evaluation of Blocked Stencil Computations on GPUs
inferred← citeshttps://doi.org/10.1145/3650200.3656611openalex-snapshot
Stencil Computation with Vector Outer Product
inferred← citeshttps://doi.org/10.1145/3710848.3710886openalex-snapshot
Jigsaw: Toward Conflict-free Vectorized Stencil Computation by Tessellating Swizzled Registers
inferred← citeshttps://doi.org/10.11606/t.3.2021.tde-18052021-154710openalex-snapshot
ASLI schenes as a kernel convolved way to optimize stencil computation.
inferred← citeshttps://doi.org/10.1177/1094342017691876openalex-snapshot
On the arithmetic intensity of high-order finite-volume discretizations for hyperbolic systems of conservation laws
inferred← citeshttps://doi.org/10.1177/10943420241268288openalex-snapshot
Bricks: A high-performance portability layer for computations on block-structured grids
inferred← citeshttps://doi.org/10.18122/td/1654/boisestateopenalex-snapshot
Polyhedral+Dataflow Graphs
inferred← citeshttps://doi.org/10.3390/electronics11010038openalex-snapshot
On the Transformation Optimization for Stencil Computation
inferred← citeshttps://doi.org/10.3934/dcds.2016.36.4247openalex-snapshot
High-order finite-volume methods on locally-structured grids
inferred← citeshttps://doi.org/10.48550/arxiv.1606.07676openalex-snapshot
Message-Combining Algorithms for Isomorphic, Sparse Collective Communication
inferred← citeshttps://doi.org/10.48550/arxiv.2103.09235openalex-snapshot
Reducing Redundancy in Data Organization and Arithmetic Calculation for Stencil Computations
inferred← citeshttps://doi.org/10.70675/7954fab8ze891z46eeza55az2fc9177718dcopenalex-snapshot
Design space exploration of image processing algorithms on FPGAs
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