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A Dual-Consistency Cache Coherence Protocol
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4614-8745-6_3openalex-snapshot
Intel® Xeon Phi™ Coprocessors
inferredcites →https://doi.org/10.1007/bf01407931openalex-snapshot
Dataflow analysis of array and scalar references
inferredcites →https://doi.org/10.1057/jors.1987.94openalex-snapshot
Theory of Linear and Integer Programming
inferredcites →https://doi.org/10.1109/2.546611openalex-snapshot
Shared memory consistency models: a tutorial
inferredcites →https://doi.org/10.1109/cgo.2004.1281665openalex-snapshot
LLVM: a compilation framework for lifelong program analysis & transformation
inferredcites →https://doi.org/10.1109/hpca.2014.6835927openalex-snapshot
TSO-CC: Consistency directed cache coherence for TSO
inferredcites →https://doi.org/10.1109/iccd.2009.5413143openalex-snapshot
Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling
inferredcites →https://doi.org/10.1109/icpp.2013.70openalex-snapshot
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/isca.1990.134502openalex-snapshot
Weak ordering-a new definition
inferredcites →https://doi.org/10.1109/isca.1995.524548openalex-snapshot
Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.2012.6237045openalex-snapshot
End-to-end sequential consistency
inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot
GARNET: A detailed on-chip network model inside a full-system simulator
inferredcites →https://doi.org/10.1109/micro.2012.39openalex-snapshot
Spatiotemporal Coherence Tracking
inferredcites →https://doi.org/10.1109/mm.2010.82openalex-snapshot
SARC Coherence: Scaling Directory Cache Coherence in Performance and Power
inferredcites →https://doi.org/10.1109/pact.2011.11openalex-snapshot
POPS: Coherence Protocol Optimization for Both Private and Shared Data
inferredcites →https://doi.org/10.1109/pact.2011.21openalex-snapshot
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
inferredcites →https://doi.org/10.1109/tc.2010.155openalex-snapshot
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
inferredcites →https://doi.org/10.1109/tc.2011.241openalex-snapshot
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/17356.17404openalex-snapshot
A class of compatible cache consistency protocols and their support by the IEEE futurebus
inferredcites →https://doi.org/10.1145/1854273.1854335openalex-snapshot
Compiler-assisted data distribution for chip multiprocessors
inferredcites →https://doi.org/10.1145/1988915.1988922openalex-snapshot
Extended sequential reasoning for data-race-free programs
inferredcites →https://doi.org/10.1145/2000064.2000076openalex-snapshot
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
inferredcites →https://doi.org/10.1145/2209249.2209269openalex-snapshot
Why on-chip cache coherence is here to stay
inferredcites →https://doi.org/10.1145/2366231.2337220openalex-snapshot
End-to-end sequential consistency
inferredcites →https://doi.org/10.1145/2370816.2370853openalex-snapshot
Complexity-effective multicore coherence
inferredcites →https://doi.org/10.1145/2485922.2485968openalex-snapshot
A new perspective for efficient virtual-cache coherence
inferredcites →https://doi.org/10.1145/2540708.2540739openalex-snapshot
Multi-grain coherence directories
inferredcites →https://doi.org/10.2307/253980openalex-snapshot
Theory of Linear and Integer Programming
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.3871openalex-snapshot
A dedicated private‐shared cache design for scalable multiprocessors
inferred← citeshttps://doi.org/10.1109/cgo.2017.7863725openalex-snapshot
Automatic detection of extended data-race-free regions
inferred← citeshttps://doi.org/10.1109/escience.2015.28openalex-snapshot
Early Experiences with Separate Caches for Private and Shared Data
inferred← citeshttps://doi.org/10.1109/pact.2015.37openalex-snapshot
RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions
inferred← citeshttps://doi.org/10.1109/tpds.2016.2528241openalex-snapshot
A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence
inferred← citeshttps://doi.org/10.1109/tpds.2017.2658576openalex-snapshot
TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs
inferred← citeshttps://doi.org/10.1109/tpds.2017.2720744openalex-snapshot
Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics
inferred← citeshttps://doi.org/10.1109/tpds.2017.2771509openalex-snapshot
Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation
inferred← citeshttps://doi.org/10.1109/tpds.2017.2782808openalex-snapshot
TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction
inferred← citeshttps://doi.org/10.1145/3579990.3580013openalex-snapshot
WARDen: Specializing Cache Coherence for High-Level Parallel Languages
inferred← citeshttps://doi.org/10.21123/bsj.14.1.219-230openalex-snapshot
Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State
inferred← citeshttps://doi.org/10.21123/bsj.2017.14.1.0219openalex-snapshot
Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State
inferred← citeshttps://doi.org/10.23940/ijpe.18.01.p19.178185openalex-snapshot
A Cache Consistency Protocol with Improved Architecture
inferred← citeshttps://doi.org/10.30684/etj.34.6b.20openalex-snapshot
Proposal New Cache Coherence Protocol to Optimize CPU Time through Simulation Caches
inferred← citeshttps://doi.org/10.4995/thesis/10251/86136openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.4995/thesis/10251/86187openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.5555/3195638.3195678openalex-snapshot
Racer: TSO consistency via race detection
inferred← citeshttps://doi.org/10.5821/dissertation-2117-336238openalex-snapshot
Runtime-assisted coherent caching
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