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Spatiotemporal Coherence Tracking
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-3604-8_9openalex-snapshot
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes*
inferredcites →https://doi.org/10.1109/12.752660openalex-snapshot
Randomized cache placement for eliminating conflicts
inferredcites →https://doi.org/10.1109/date.2012.6176456openalex-snapshot
Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores
inferredcites →https://doi.org/10.1109/hotchips.2006.7477874openalex-snapshot
Niagara-2: A highly threaded server-on-a-chip
inferredcites →https://doi.org/10.1109/hpca.2011.5749726openalex-snapshot
Cuckoo directory: A scalable directory for many-core systems
inferredcites →https://doi.org/10.1109/hpca.2012.6168950openalex-snapshot
SCD: A scalable coherence directory with flexible sharer set encoding
inferredcites →https://doi.org/10.1109/isca.1988.5238openalex-snapshot
An evaluation of directory schemes for cache coherence
inferredcites →https://doi.org/10.1109/isca.1993.698558openalex-snapshot
Acase For Two-way Skewed-associative Caches
inferredcites →https://doi.org/10.1109/isca.2000.854398openalex-snapshot
Piranha: a scalable architecture based on single-chip multiprocessing
inferredcites →https://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferredcites →https://doi.org/10.1109/mm.2006.79openalex-snapshot
SimFlex: Statistical Sampling of Computer System Simulation
inferredcites →https://doi.org/10.1109/mm.2010.31openalex-snapshot
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
inferredcites →https://doi.org/10.1145/1080695.1069991openalex-snapshot
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/1669112.1669166openalex-snapshot
A tagless coherence directory
inferredcites →https://doi.org/10.1145/2000064.2000076openalex-snapshot
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
inferredcites →https://doi.org/10.1145/285930.285995openalex-snapshot
An evaluation of directory schemes for cache coherence
inferredcites →https://doi.org/10.1145/291069.291067openalex-snapshot
Performance of database workloads on shared-memory systems with out-of-order processors
inferredcites →https://doi.org/10.5555/2492708.2492829openalex-snapshot
Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-662-44491-7_1openalex-snapshot
Fusion Coherence: Scalable Cache Coherence for Heterogeneous Kilo-Core System
inferred← citeshttps://doi.org/10.1007/s11227-014-1288-5openalex-snapshot
PS-Cache: an energy-efficient cache design for chip multiprocessors
inferred← citeshttps://doi.org/10.1007/s11227-018-02735-zopenalex-snapshot
Dynamic directory table with victim cache: on-demand allocation of directory entries for active shared cache blocks
inferred← citeshttps://doi.org/10.1007/s11227-023-05559-8openalex-snapshot
Scalable short-entry dual-grain coherence directories with flexible region granularity
inferred← citeshttps://doi.org/10.1007/s11390-014-1459-0openalex-snapshot
DEAM: Decoupled, Expressive, Area-Efficient Metadata Cache
inferred← citeshttps://doi.org/10.1016/j.jpdc.2016.12.020openalex-snapshot
An adaptive cache coherence protocol: Trading storage for traffic
inferred← citeshttps://doi.org/10.1109/escience.2015.28openalex-snapshot
Early Experiences with Separate Caches for Private and Shared Data
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835928openalex-snapshot
Stash directory: A scalable directory for many-core coherence
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056032openalex-snapshot
Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056033openalex-snapshot
Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056065openalex-snapshot
Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446089openalex-snapshot
Selective GPU caches to eliminate CPU-GPU HW cache coherence
inferred← citeshttps://doi.org/10.1109/hpca.2017.24openalex-snapshot
Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00032openalex-snapshot
Zero Directory Eviction Victim: Unbounded Coherence Directory and Core Cache Isolation
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357165openalex-snapshot
Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems
inferred← citeshttps://doi.org/10.1109/icgciot.2015.7380439openalex-snapshot
Comparison of significant issues in multicore cache coherence
inferred← citeshttps://doi.org/10.1109/icpp.2013.70openalex-snapshot
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/icsict55466.2022.9963143openalex-snapshot
RG_VIPS: A Simple Cache Coherence Protocol Based on Region-Grain Directories
inferred← citeshttps://doi.org/10.1109/icsict55466.2022.9963419openalex-snapshot
SS-DGD: Scalable Short-Entry Dual-Grain Coherence Directoris
inferred← citeshttps://doi.org/10.1109/ipdps.2015.43openalex-snapshot
A Dual-Consistency Cache Coherence Protocol
inferred← citeshttps://doi.org/10.1109/nas.2014.43openalex-snapshot
iCHAT: Inter-cache Hardware-Assistant Data Transfer for Heterogeneous Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/pact.2013.6618826openalex-snapshot
Generating efficient data movement code for heterogeneous architectures with distributed-memory
inferred← citeshttps://doi.org/10.1109/pact.2015.23openalex-snapshot
An Efficient, Self-Contained, On-chip Directory: DIR1-SISD
inferred← citeshttps://doi.org/10.1109/sc.2018.00038openalex-snapshot
Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs
inferred← citeshttps://doi.org/10.1109/tc.2015.2435790openalex-snapshot
Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking
inferred← citeshttps://doi.org/10.1109/tc.2017.2676768openalex-snapshot
Adaptive Coherence Granularity for Multi-Socket Systems
inferred← citeshttps://doi.org/10.1109/tpds.2015.2412139openalex-snapshot
Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2016.2528241openalex-snapshot
A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence
inferred← citeshttps://doi.org/10.1109/tpds.2017.2658576openalex-snapshot
TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs
inferred← citeshttps://doi.org/10.1109/tpds.2017.2700307openalex-snapshot
Prophet: A Parallel Instruction-Oriented Many-Core Simulator
inferred← citeshttps://doi.org/10.1109/tpds.2017.2782808openalex-snapshot
TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction
inferred← citeshttps://doi.org/10.1109/tpds.2019.2917185openalex-snapshot
Way Combination for an Adaptive and Scalable Coherence Directory
inferred← citeshttps://doi.org/10.1109/tpds.2022.3217956openalex-snapshot
Tag-Sharer-Fusion Directory: A Scalable Coherence Directory With Flexible Entry Formats
inferred← citeshttps://doi.org/10.1145/2540708.2540739openalex-snapshot
Multi-grain coherence directories
inferred← citeshttps://doi.org/10.1145/2540708.2540747openalex-snapshot
Heterogeneous system coherence for integrated CPU-GPU systems
inferred← citeshttps://doi.org/10.1145/2749469.2750411openalex-snapshot
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
inferred← citeshttps://doi.org/10.1145/2790301openalex-snapshot
The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence
inferred← citeshttps://doi.org/10.1145/2872887.2750411openalex-snapshot
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
inferred← citeshttps://doi.org/10.1145/2925426.2926270openalex-snapshot
Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures
inferred← citeshttps://doi.org/10.1145/2989081.2989092openalex-snapshot
Software Assisted Hardware Cache Coherence for Heterogeneous Processors
inferred← citeshttps://doi.org/10.1145/3092702openalex-snapshot
Using Multicore Reuse Distance to Study Coherence Directories
inferred← citeshttps://doi.org/10.1145/3462775openalex-snapshot
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures
inferred← citeshttps://doi.org/10.13016/m2x91hopenalex-snapshot
Studying the Impact of Multicore Processor Scaling on Cache Coherence Directories via Reuse Distance Analysis
inferred← citeshttps://doi.org/10.23919/date.2019.8714723openalex-snapshot
Lightweight hardware support for selective coherence in heterogeneous manycore accelerators
inferred← citeshttps://doi.org/10.4995/thesis/10251/79551openalex-snapshot
Improving Energy and Area Scalability of the Cache Hierarchy in CMPs
inferred← citeshttps://doi.org/10.4995/thesis/10251/86136openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.4995/thesis/10251/86187openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.5075/epfl-thesis-6631openalex-snapshot
Multi-Gigabyte On-Chip DRAM Caches for Servers
inferred← citeshttps://doi.org/10.5555/2755753.2755792openalex-snapshot
SelectDirectory: a selective directory for cache coherence in many-core architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-336238openalex-snapshot
Runtime-assisted coherent caching
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96004openalex-snapshot
Transparent management of scratchpad memories in shared memory programming models
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