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Deflection Containment for Bufferless Network-on-Chips
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/aspdac.2008.4484015openalex-snapshot
Run-time power gating of on-chip routers using look-ahead routing
inferredcites →https://doi.org/10.1109/e3s.2013.6705860openalex-snapshot
A landscape of the new dark silicon design regime
inferredcites →https://doi.org/10.1109/hpca.2009.4798251openalex-snapshot
Express Cube Topologies for on-Chip Interconnects
inferredcites →https://doi.org/10.1109/hpca.2011.5749724openalex-snapshot
CHIPPER: A low-complexity bufferless deflection router
inferredcites →https://doi.org/10.1109/hpca.2015.7056048openalex-snapshot
Power punch: Towards non-blocking power-gating of NoC routers
inferredcites →https://doi.org/10.1109/isca.1990.134508openalex-snapshot
Virtual-channel flow control
inferredcites →https://doi.org/10.1109/isca.2004.1310759openalex-snapshot
Evaluation of the raw microprocessor: an exposed-wire-delay architecture for ILP and streams
inferredcites →https://doi.org/10.1109/isca.2008.19openalex-snapshot
Technology-Driven, Highly-Scalable Dragonfly Topology
inferredcites →https://doi.org/10.1109/l-ca.2012.22openalex-snapshot
Clumsy Flow Control for High-Throughput Bufferless On-Chip Networks
inferredcites →https://doi.org/10.1109/micro.2004.28openalex-snapshot
Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
inferredcites →https://doi.org/10.1109/micro.2007.15openalex-snapshot
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
inferredcites →https://doi.org/10.1109/micro.2007.29openalex-snapshot
Flattened Butterfly Topology for On-Chip Networks
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/mm.2003.1261386openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous trips architecture
inferredcites →https://doi.org/10.1109/mm.2007.4378780openalex-snapshot
On-Chip Interconnection Architecture of the Tile Processor
inferredcites →https://doi.org/10.1109/mm.2007.4378783openalex-snapshot
A 5-GHz Mesh Interconnect for a Teraflops Processor
inferredcites →https://doi.org/10.1109/mm.2013.90openalex-snapshot
A Landscape of the New Dark Silicon Design Regime
inferredcites →https://doi.org/10.1109/nocs.2010.10openalex-snapshot
Evaluating Bufferless Flow Control for On-chip Networks
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/nocs.2012.8openalex-snapshot
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
inferredcites →https://doi.org/10.1109/nocs.2014.7008756openalex-snapshot
Extending bufferless on-chip networks to high-throughput workloads
inferredcites →https://doi.org/10.1109/sbac-pad.2014.31openalex-snapshot
Design and Evaluation of Hierarchical Rings with Deflection Routing
inferredcites →https://doi.org/10.1145/1028176.1006733openalex-snapshot
Evaluation of the Raw Microprocessor
inferredcites →https://doi.org/10.1145/1394608.1382129openalex-snapshot
Technology-Driven, Highly-Scalable Dragonfly Topology
inferredcites →https://doi.org/10.1145/1468075.1468121openalex-snapshot
Sorting networks and their applications
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/2463209.2488779openalex-snapshot
A heterogeneous multiple network-on-chip design
inferredcites →https://doi.org/10.1145/378995.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-021-03850-0openalex-snapshot
Optimal port allocation scheme for deflection-routed networks-on-chip
inferred← citeshttps://doi.org/10.1109/access.2021.3111294openalex-snapshot
SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router
inferred← citeshttps://doi.org/10.1109/icscsa64454.2024.00109openalex-snapshot
Design and Implementation of Novel Buffer-less NoC Router
inferred← citeshttps://doi.org/10.1109/ised.2018.8704012openalex-snapshot
ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs
inferred← citeshttps://doi.org/10.1109/tcad.2019.2907909openalex-snapshot
Enhancing Network-on-Chip Performance by Reusing Trace Buffers
inferred← citeshttps://doi.org/10.1145/3073763.3073767openalex-snapshot
A survey of low power NoC design techniques
inferred← citeshttps://doi.org/10.1515/joc-2024-0264openalex-snapshot
Bufferless NoC router design for optical networks-on-chip
inferred← citeshttps://doi.org/10.17577/ijertv9is070088openalex-snapshot
Power Optimization Techniques for NOC
inferred← citeshttps://doi.org/10.3390/jlpea7020014openalex-snapshot
Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer
inferred← citeshttps://doi.org/10.70675/6ee3d5c1zfa27z4edbz8ff2z9ac3b7eebfaaopenalex-snapshot
Exploration of multicore systems based on silicon integrated communication networks
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