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Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Large System Performance of SPEC OMP2001 Benchmarks
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Prophet: A Parallel Instruction-Oriented Many-Core Simulator
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A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2420315openalex-snapshot
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2536747openalex-snapshot
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2603164openalex-snapshot
A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
inferred← citeshttps://doi.org/10.1109/uic-atc.2017.8397629openalex-snapshot
The time-varying nature of cache utilization: A case study on the Mantevo and Apex benchmarks
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2015.7314413openalex-snapshot
Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM
inferred← citeshttps://doi.org/10.1109/vlsid60093.2024.00067openalex-snapshot
Early Execution for Soft Error Detection
inferred← citeshttps://doi.org/10.1109/wscad.2018.00033openalex-snapshot
Phase Detection and Analysis among Multiple Program Inputs
inferred← citeshttps://doi.org/10.1145/1080695.1070014openalex-snapshot
Computing Architectural Vulnerability Factors for Address-Based Structures
inferred← citeshttps://doi.org/10.1145/1088149.1088153openalex-snapshot
A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks
inferred← citeshttps://doi.org/10.1145/1140103.1140303openalex-snapshot
Automatic logging of operating system effects to guide application-level architecture simulation
inferred← citeshttps://doi.org/10.1145/1140277.1140303openalex-snapshot
Automatic logging of operating system effects to guide application-level architecture simulation
inferred← citeshttps://doi.org/10.1145/1176254.1176301openalex-snapshot
Phase guided sampling for efficient parallel application simulation
inferred← citeshttps://doi.org/10.1145/1183401.1183410openalex-snapshot
Selective predicate prediction for out-of-order processors
inferred← citeshttps://doi.org/10.1145/1187976.1187978openalex-snapshot
Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques
inferred← citeshttps://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferred← citeshttps://doi.org/10.1145/1400751.1400799openalex-snapshot
Distributed order scheduling and its application to multi-core dram controllers
inferred← citeshttps://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferred← citeshttps://doi.org/10.1145/1555815.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferred← citeshttps://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferred← citeshttps://doi.org/10.1145/1669112.1669154openalex-snapshot
Coordinated control of multiple prefetchers in multi-core systems
inferred← citeshttps://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferred← citeshttps://doi.org/10.1145/1735970.1736058openalex-snapshot
Fairness via source throttling
inferred← citeshttps://doi.org/10.1145/1735971.1736058openalex-snapshot
Fairness via source throttling
inferred← citeshttps://doi.org/10.1145/1736020.1736058openalex-snapshot
Fairness via source throttling
inferred← citeshttps://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferred← citeshttps://doi.org/10.1145/1816038.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferred← citeshttps://doi.org/10.1145/2000064.2000081openalex-snapshot
Prefetch-aware shared resource management for multi-core systems
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