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MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Efficiency Optimization of Trainable Feature Extractors for a Consumer Platform
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Gradient-based learning applied to document recognition
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Partially reconfigurable interconnection network for dynamically reprogrammable resource array
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Rich Feature Hierarchies for Accurate Object Detection and Semantic Segmentation
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Customizable Compression Architecture for Efficient Configuration in CGRAs
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CNP: An FPGA-based processor for Convolutional Networks
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Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures
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Classification of Massively Parallel Computer Architectures
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EIE: Efficient Inference Engine on Compressed Deep Neural Network
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Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
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39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation
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Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells
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Neural Acceleration for General-Purpose Approximate Programs
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Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs
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TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs
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Online memory compression for embedded systems
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Dark silicon and the end of multicore scaling
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A defect-tolerant accelerator for emerging high-performance applications
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Base-delta-immediate compression
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Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
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ImageNet classification with deep convolutional neural networks
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Caffe: Convolutional Architecture for Fast Feature Embedding
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Going Deeper with Convolutions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A Heterogeneous and Reconfigurable Embedded Architecture for Energy-Efficient Execution of Convolutional Neural Networks
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A Reconfigurable Streaming Processor for Real-Time Low-Power Execution of Convolutional Neural Networks at the Edge
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Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks
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eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex
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Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study
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Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators
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From DNNs to GANs: Review of efficient hardware architectures for deep learning
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