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Neural Acceleration for General-Purpose Approximate Programs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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FPGA Implementations of Neural Networks
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FPGA Implementations of Neural Networks – A Survey of a Decade of Progress
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Multifold Acceleration of Neural Network Computations Using GPU
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Learning Internal Representations by Error Propagation
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GPU implementation of neural networks
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An analog neural network processor with programmable topology
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Estimations of error bounds for neural-network function approximators
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Parallel digital implementations of neural networks
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A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications
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Ultra-Efficient (Embedded) SOC Architectures based on Probabilistic CMOS (PCMOS) Technology
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ERSA: Error Resilient System Architecture for probabilistic applications
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Scalable stochastic processors
inferredcites →https://doi.org/10.1109/hpca.2009.4798266openalex-snapshot
Bridging the computation gap between programmable processors and hardwired accelerators
inferredcites →https://doi.org/10.1109/hpca.2011.5749755openalex-snapshot
Dynamically Specialized Datapaths for energy efficient computing
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Learning on an analog VLSI neural network chip
inferredcites →https://doi.org/10.1109/iiswc.2012.6402898openalex-snapshot
BenchNN: On the broad potential application scope of hardware neural network accelerators
inferredcites →https://doi.org/10.1109/ijcnn.2008.4633828openalex-snapshot
Wafer-scale integration of analog neural networks
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Hardware spiking neurons design: Analog or digital?
inferredcites →https://doi.org/10.1109/isca.2012.6237031openalex-snapshot
A defect-tolerant accelerator for emerging high-performance applications
inferredcites →https://doi.org/10.1109/iscas.2006.1693199openalex-snapshot
Neural Network Stream Processing Core (NnSP) for Embedded Systems
inferredcites →https://doi.org/10.1109/isscc.1991.689119openalex-snapshot
An Analog Neural Network Processor With Programmable Network Topology
inferredcites →https://doi.org/10.1109/micro.2004.5openalex-snapshot
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2007.33openalex-snapshot
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
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Dark Silicon and the End of Multicore Scaling
inferredcites →https://doi.org/10.1109/tc.2005.119openalex-snapshot
Fuzzy Memoization for Floating-Point Multimedia Applications
inferredcites →https://doi.org/10.1109/tc.2010.121openalex-snapshot
Energy-Efficient Floating-Point Unit Design
inferredcites →https://doi.org/10.1109/tc.2012.132openalex-snapshot
Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures
inferredcites →https://doi.org/10.1145/1815961.1815968openalex-snapshot
Understanding sources of inefficiency in general-purpose chips
inferredcites →https://doi.org/10.1145/192724.192749openalex-snapshot
A high-performance microarchitecture with hardware-programmable functional units
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Automatic abstraction and fault tolerance in cortical microachitectures
inferredcites →https://doi.org/10.1145/2000064.2000108openalex-snapshot
Dark silicon and the end of multicore scaling
inferredcites →https://doi.org/10.1145/2025113.2025133openalex-snapshot
Managing performance vs. accuracy trade-offs with loop perforation
inferredcites →https://doi.org/10.1145/2150976.2151008openalex-snapshot
Architecture support for disciplined approximate programming
inferredcites →https://doi.org/10.1145/2155620.2155623openalex-snapshot
Bundled execution of recurring traces for energy-efficient general purpose processing
inferredcites →https://doi.org/10.1145/2366231.2337200openalex-snapshot
A defect-tolerant accelerator for emerging high-performance applications
inferredcites →https://doi.org/10.1145/313817.313834openalex-snapshot
Energy-efficient signal processing via algorithmic noise-tolerance
inferredcites →https://doi.org/10.21236/ada164453openalex-snapshot
Learning Internal Representations by Error Propagation
inferredcites →https://doi.org/10.5555/1870926.1871008openalex-snapshot
Scalable stochastic processors
inferredcites →https://doi.org/10.5555/1870926.1871302openalex-snapshot
ERSA: error resilient system architecture for probabilistic applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware Accelerators for Classification of Thoracic Disorders: A Survey
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High Performance Static Segment On-Chip Memory for Image Processing Applications
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Research on Field Programmable Neuron Array (FPNA) Based on Reusable ANN Neurons
inferred← citeshttps://doi.org/10.1109/ictck.2015.7582713openalex-snapshot
Do we need approximate-aware cache in dark silicon era?
inferred← citeshttps://doi.org/10.1109/iiswc.2014.6983050openalex-snapshot
MachSuite: Benchmarks for accelerator design and customized architectures
inferred← citeshttps://doi.org/10.1109/iiswc.2017.8167765openalex-snapshot
Approximeter: Automatically finding and quantifying code sections for approximation
inferred← citeshttps://doi.org/10.1109/iiswc47752.2019.9042035openalex-snapshot
An Overflow-free Quantized Memory Hierarchy in General-purpose Processors
inferred← citeshttps://doi.org/10.1109/iiswc50251.2020.00035openalex-snapshot
Selective Event Processing for Energy Efficient Mobile Gaming with SNIP
inferred← citeshttps://doi.org/10.1109/ijcnn.2013.6706775openalex-snapshot
Routing bandwidth model for feed forward neural networks on multicore neuromorphic architectures
inferred← citeshttps://doi.org/10.1109/ijcnn.2013.6707074openalex-snapshot
Exploring the design space of specialized multicore neural processors
inferred← citeshttps://doi.org/10.1109/ijcnn.2014.6889893openalex-snapshot
Enabling back propagation training of memristor crossbar neuromorphic processors
inferred← citeshttps://doi.org/10.1109/ims3tw.2017.7995210openalex-snapshot
Test and reliability in approximate computing
inferred← citeshttps://doi.org/10.1109/ipdps.2014.54openalex-snapshot
Algorithmic Time, Energy, and Power on Candidate HPC Compute Building Blocks
inferred← citeshttps://doi.org/10.1109/ipdps.2017.49openalex-snapshot
ATM: Approximate Task Memoization in the Runtime System
inferred← citeshttps://doi.org/10.1109/ipdps.2017.59openalex-snapshot
MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.116openalex-snapshot
Cache-Aware Approximate Computing for Decision Tree Learning
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.183openalex-snapshot
Assessing Multi-task Placement Algorithms in RCUs
inferred← citeshttps://doi.org/10.1109/isca.2014.6853196openalex-snapshot
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
inferred← citeshttps://doi.org/10.1109/isca.2014.6853213openalex-snapshot
General-purpose code acceleration with limited-precision analog computation
inferred← citeshttps://doi.org/10.1109/isca.2016.13openalex-snapshot
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory
inferred← citeshttps://doi.org/10.1109/isca.2016.16openalex-snapshot
Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration
inferred← citeshttps://doi.org/10.1109/isca.2016.39openalex-snapshot
Production-Run Software Failure Diagnosis via Adaptive Communication Tracking
inferred← citeshttps://doi.org/10.1109/isca.2016.42openalex-snapshot
Cambricon: An Instruction Set Architecture for Neural Networks
inferred← citeshttps://doi.org/10.1109/isca.2016.55openalex-snapshot
Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units
inferred← citeshttps://doi.org/10.1109/isca.2018.00038openalex-snapshot
Scaling Datacenter Accelerators with Compute-Reuse Architectures
inferred← citeshttps://doi.org/10.1109/isca.2018.00047openalex-snapshot
RoboX: An End-to-End Solution to Accelerate Autonomous Control in Robotics
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00051openalex-snapshot
η-LSTM: Co-Designing Highly-Efficient Large LSTM Training via Exploiting Memory-Saving and Architectural Design Opportunities
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00062openalex-snapshot
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00047openalex-snapshot
Tartan: Microarchitecting a Robotic Processor
inferred← citeshttps://doi.org/10.1109/iscaie.2018.8405486openalex-snapshot
A promising power-saving technique: Approximate computing
inferred← citeshttps://doi.org/10.1109/iscas.2015.7168938openalex-snapshot
A case of precision-tunable STT-RAM memory design for approximate neural network
inferred← citeshttps://doi.org/10.1109/iscas.2015.7169195openalex-snapshot
Neural approximating architecture targeting multiple application domains
inferred← citeshttps://doi.org/10.1109/iscas.2016.7527186openalex-snapshot
Heterogeneous systems with reconfigurable neuromorphic computing accelerators
inferred← citeshttps://doi.org/10.1109/iscas.2018.8350918openalex-snapshot
A Multi-Mode Visual Recognition Hardware Accelerator for AR/MR Glasses
inferred← citeshttps://doi.org/10.1109/iscas.2018.8350956openalex-snapshot
An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180840openalex-snapshot
Can We Securely Use Approximate Computing?
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9181071openalex-snapshot
RISC-V2: A Scalable RISC-V Vector Processor
inferred← citeshttps://doi.org/10.1109/isgt-asia.2019.8881481openalex-snapshot
Fusion of Multi-time Section Measurements for State Estimation of Power System
inferred← citeshttps://doi.org/10.1109/islped.2013.6629302openalex-snapshot
Memristor-based approximated computation
inferred← citeshttps://doi.org/10.1109/ispass.2015.7095806openalex-snapshot
Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation
inferred← citeshttps://doi.org/10.1109/ispass51385.2021.00048openalex-snapshot
TPUPoint: Automatic Characterization of Hardware-Accelerated Machine-Learning Behavior for Cloud Computing
inferred← citeshttps://doi.org/10.1109/ispass55109.2022.00024openalex-snapshot
RTRBench: A Benchmark Suite for Real-Time Robotics
inferred← citeshttps://doi.org/10.1109/ispass61541.2024.00038openalex-snapshot
Accel-Bench: Exploring the Potential of Programming Using Hardware-Accelerated Functions
inferred← citeshttps://doi.org/10.1109/isqed.2018.8357263openalex-snapshot
Program acceleration using nearest distance associative search
inferred← citeshttps://doi.org/10.1109/isqed.2019.8697679openalex-snapshot
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
inferred← citeshttps://doi.org/10.1109/issre.2016.49openalex-snapshot
Approximate Lock: Trading off Accuracy for Performance by Skipping Critical Sections
inferred← citeshttps://doi.org/10.1109/isvlsi.2018.00051openalex-snapshot
Hardware Implementation of Reconfigurable Separable Convolution
inferred← citeshttps://doi.org/10.1109/isvlsi.2018.00110openalex-snapshot
A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00106openalex-snapshot
Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps
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Associative Memristive Memory for Approximate Computing in GPUs
inferred← citeshttps://doi.org/10.1109/jetcas.2018.2852701openalex-snapshot
A Hybrid Approximate Computing Approach for Associative In-Memory Processors
inferred← citeshttps://doi.org/10.1109/jproc.2015.2435018openalex-snapshot
Evolution of Memory Architecture
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Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software
inferred← citeshttps://doi.org/10.1109/jproc.2020.2977722openalex-snapshot
Self-Aware Neural Network Systems: A Survey and New Perspective
inferred← citeshttps://doi.org/10.1109/jproc.2020.2999613openalex-snapshot
A Survey of Testing Techniques for Approximate Integrated Circuits
inferred← citeshttps://doi.org/10.1109/jproc.2020.3020792openalex-snapshot
Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx
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Efficient AI System Design With Cross-Layer Approximate Computing
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A Neural Network-Based Model of Radio Frequency Energy Harvesting Characteristics in a Self-Powered Food Monitoring System
inferred← citeshttps://doi.org/10.1109/latw.2018.8347241openalex-snapshot
A review of approximate computing techniques towards fault mitigation in HW/SW systems
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Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse
inferred← citeshttps://doi.org/10.1109/les.2017.2746742openalex-snapshot
Nvalt: Nonvolatile Approximate Lookup Table for GPU Acceleration
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A Taxonomy of General Purpose Approximate Computing Techniques
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Multi-UAV Situational Awareness via Distributed and Approximate Computing Techniques
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Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache Hierarchy
inferred← citeshttps://doi.org/10.1109/mdat.2015.2487218openalex-snapshot
Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing
inferred← citeshttps://doi.org/10.1109/mdat.2015.2497334openalex-snapshot
CIRCA-GPUs: Increasing Instruction Reuse Through Inexact Computing in GP-GPUs
inferred← citeshttps://doi.org/10.1109/mdat.2015.2501306openalex-snapshot
Quality Control for Approximate Accelerators by Error Prediction
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Approximate Computing: A Survey
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AxBench: A Multiplatform Benchmark Suite for Approximate Computing
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A Survey on Architecture Advances Enabled by Emerging Beyond-CMOS Technologies
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DaDianNao: A Machine-Learning Supercomputer
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