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Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.822565openalex-snapshot
Probabilistic loop scheduling for applications with uncertain execution time
inferredcites →https://doi.org/10.1109/date.2010.5456923openalex-snapshot
Increasing PCM main memory lifetime
inferredcites →https://doi.org/10.1109/date.2010.5457219openalex-snapshot
A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)
inferredcites →https://doi.org/10.1109/date.2010.5457221openalex-snapshot
Energy- and endurance-aware design of phase change memory caches
inferredcites →https://doi.org/10.1109/date.2011.5763127openalex-snapshot
Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory
inferredcites →https://doi.org/10.1109/icpads.2005.196openalex-snapshot
Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems
inferredcites →https://doi.org/10.1109/icws.2011.21openalex-snapshot
Ontology-Driven Query Expansion Using Map/Reduce Framework to Facilitate Federated Queries
inferredcites →https://doi.org/10.1109/iedm.2005.1609379openalex-snapshot
A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram
inferredcites →https://doi.org/10.1109/mm.2006.82openalex-snapshot
The M5 Simulator: Modeling Networked Systems
inferredcites →https://doi.org/10.1109/sasp.2010.5521139openalex-snapshot
Minimizing write activities to non-volatile memory via scheduling and recomputation
inferredcites →https://doi.org/10.1109/tcad.2010.2097307openalex-snapshot
Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation
inferredcites →https://doi.org/10.1109/tvlsi.2005.859478openalex-snapshot
Compiler-guided leakage optimization for banked scratch-pad memories
inferredcites →https://doi.org/10.1109/vlsisoc.2010.5642609openalex-snapshot
Optimal scheduling to minimize non-volatile memory access time with hardware cache
inferredcites →https://doi.org/10.1145/1148015.1148016openalex-snapshot
Design space exploration for 3D architectures
inferredcites →https://doi.org/10.1145/1366110.1366204openalex-snapshot
A low-power phase change memory based hybrid cache architecture
inferredcites →https://doi.org/10.1145/1391469.1391610openalex-snapshot
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferredcites →https://doi.org/10.1145/1785481.1785503openalex-snapshot
Write activity reduction on flash main memory via smart victim cache
inferredcites →https://doi.org/10.1145/1837274.1837363openalex-snapshot
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation
inferredcites →https://doi.org/10.1145/2442116.2442127openalex-snapshot
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
inferredcites →https://doi.org/10.1145/951710.951747openalex-snapshot
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
inferredcites →https://doi.org/10.1145/951746.951747openalex-snapshot
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10617-014-9151-8openalex-snapshot
Design exploration of a NVM based hybrid instruction memory organization for embedded platforms
inferred← citeshttps://doi.org/10.1007/s11227-017-1977-yopenalex-snapshot
An efficient cloud storage system for tele-health services
inferred← citeshttps://doi.org/10.1007/s11227-017-2099-2openalex-snapshot
Advances in next era cloud-empowered computing and techniques
inferred← citeshttps://doi.org/10.1109/access.2018.2887024openalex-snapshot
Dynamic Data Allocation and Task Scheduling on Multiprocessor Systems With NVM-Based SPM
inferred← citeshttps://doi.org/10.1109/tc.2013.11openalex-snapshot
Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories
inferred← citeshttps://doi.org/10.1109/tvlsi.2012.2202700openalex-snapshot
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory
inferred← citeshttps://doi.org/10.1145/2560019openalex-snapshot
Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors
inferred← citeshttps://doi.org/10.1504/ijcaet.2016.079392openalex-snapshot
A survey of power management techniques for phase change memory
inferred← citeshttps://doi.org/10.23919/eusipco.2018.8553240openalex-snapshot
Cross-Layer Optimization in Terminals
inferred← citeshttps://doi.org/10.48550/arxiv.1309.3785openalex-snapshot
Energy Saving Techniques for Phase Change Memory (PCM)
inferred← citeshttps://doi.org/10.5555/2755753.2757118openalex-snapshot
System level exploration of a STT-MRAM based level 1 data-cache
inferred← citeshttps://doi.org/10.70675/c3a483afz5bc0z4cb2za3cdz658ab3a7f316openalex-snapshot
Transactional simulation approach for modelling performance and energy of a heterogeneous SoC memory system
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