On the public citation graph

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors

https://doi.org/10.1145/2560019
0 signed · 72 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s11265-012-0703-5openalex-snapshot
Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory
inferredcites →https://doi.org/10.1109/date.2010.5457219openalex-snapshot
A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)
inferredcites →https://doi.org/10.1109/date.2010.5457221openalex-snapshot
Energy- and endurance-aware design of phase change memory caches
inferredcites →https://doi.org/10.1109/date.2011.5763127openalex-snapshot
Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory
inferredcites →https://doi.org/10.1109/dsn.2011.5958221openalex-snapshot
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
inferredcites →https://doi.org/10.1109/edtc.1995openalex-snapshot
Proceedings the European Design and Test Conference. ED&TC 1995
inferredcites →https://doi.org/10.1109/icassp.2012.6288188openalex-snapshot
Loop scheduling optimization for chip-multiprocessors with non-volatile main memory
inferredcites →https://doi.org/10.1109/iccad.2004.1382555openalex-snapshot
Banked scratch-pad memory management for reducing leakage energy consumption
inferredcites →https://doi.org/10.1109/icpp.2011.79openalex-snapshot
Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-core Systems
inferredcites →https://doi.org/10.1109/iedm.2005.1609379openalex-snapshot
A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram
inferredcites →https://doi.org/10.1109/interact.2012.6339622openalex-snapshot
MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory
inferredcites →https://doi.org/10.1109/ipdpsw.2012.120openalex-snapshot
Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs
inferredcites →https://doi.org/10.1109/isqed.2006.115openalex-snapshot
Shared Scratch-Pad Memory Space Management
inferredcites →https://doi.org/10.1109/mm.2006.82openalex-snapshot
The M5 Simulator: Modeling Networked Systems
inferredcites →https://doi.org/10.1109/sasp.2010.5521139openalex-snapshot
Minimizing write activities to non-volatile memory via scheduling and recomputation
inferredcites →https://doi.org/10.1109/tcad.2010.2097307openalex-snapshot
Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation
inferredcites →https://doi.org/10.1109/tcsi.2011.2180441openalex-snapshot
Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices
inferredcites →https://doi.org/10.1109/tvlsi.2005.859478openalex-snapshot
Compiler-guided leakage optimization for banked scratch-pad memories
inferredcites →https://doi.org/10.1109/tvlsi.2012.2202700openalex-snapshot
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory
inferredcites →https://doi.org/10.1109/vlsisoc.2010.5642609openalex-snapshot
Optimal scheduling to minimize non-volatile memory access time with hardware cache
inferredcites →https://doi.org/10.1145/1077603openalex-snapshot
Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05
inferredcites →https://doi.org/10.1145/1148015.1148016openalex-snapshot
Design space exploration for 3D architectures
inferredcites →https://doi.org/10.1145/1151074.1151085openalex-snapshot
Dynamic allocation for scratch-pad memory using compile-time decisions
inferredcites →https://doi.org/10.1145/1366110.1366204openalex-snapshot
A low-power phase change memory based hybrid cache architecture
inferredcites →https://doi.org/10.1145/1391469.1391610openalex-snapshot
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferredcites →https://doi.org/10.1145/1594233.1594261openalex-snapshot
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
inferredcites →https://doi.org/10.1145/1629911.1630086openalex-snapshot
PDRAM
inferredcites →https://doi.org/10.1145/1687399.1687449openalex-snapshot
PCRAMsim
inferredcites →https://doi.org/10.1145/1785481.1785503openalex-snapshot
Write activity reduction on flash main memory via smart victim cache
inferredcites →https://doi.org/10.1145/1837274.1837363openalex-snapshot
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation
inferredcites →https://doi.org/10.1145/2024724.2024819openalex-snapshot
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory
inferredcites →https://doi.org/10.1145/2333660.2333738openalex-snapshot
MAC
inferredcites →https://doi.org/10.1145/2442116.2442127openalex-snapshot
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
inferredcites →https://doi.org/10.1145/502217.502221openalex-snapshot
Storage allocation for embedded processors
inferredcites →https://doi.org/10.1145/502217.502223openalex-snapshot
Heterogeneous memory management for embedded systems
inferredcites →https://doi.org/10.1145/513918.513974openalex-snapshot
Exploiting shared scratch pad memory space in embedded multiprocessor systems
inferredcites →https://doi.org/10.1145/581630openalex-snapshot
Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02
inferredcites →https://doi.org/10.1145/581888.581891openalex-snapshot
An optimal memory allocation scheme for scratch-pad-based embedded systems
inferredcites →https://doi.org/10.1145/774789.774805openalex-snapshot
Scratchpad memory
inferredcites →https://doi.org/10.1145/951710.951747openalex-snapshot
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
inferredcites →https://doi.org/10.3233/emc-2005-00051openalex-snapshot
Heap data allocation to scratch-pad memory in embedded systems
inferredcites →https://doi.org/10.5555/1233791.1233799openalex-snapshot
Heap data allocation to scratch-pad memory in embedded systems
inferredcites →https://doi.org/10.5555/1870926.1871198openalex-snapshot
Compilation of stream programs for multicore processors that incorporate scratchpad memories
inferredcites →https://doi.org/10.5555/1874620.1874803openalex-snapshot
Power and performance of read-write aware hybrid caches with non-volatile memories
inferredcites →https://doi.org/10.5555/787260.787762openalex-snapshot
Efficient utilization of scratch-pad memory in embedded processor applications

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.2139/ssrn.4519730openalex-extracted
inferred← citeshttps://doi.org/10.1007/s10617-014-9151-8openalex-snapshot
Design exploration of a NVM based hybrid instruction memory organization for embedded platforms
inferred← citeshttps://doi.org/10.1016/j.future.2022.05.005openalex-snapshot
Optimizing data placement and size configuration for morphable NVM based SPM in embedded multicore systems
inferred← citeshttps://doi.org/10.1016/j.jocs.2016.06.002openalex-snapshot
Cost-aware optimal data allocations for multiple dimensional heterogeneous memories using dynamic programming in big data
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.103022openalex-snapshot
COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
inferred← citeshttps://doi.org/10.1109/access.2018.2872762openalex-snapshot
TTEC: Data Allocation Optimization for Morphable Scratchpad Memory in Embedded Systems
inferred← citeshttps://doi.org/10.1109/cases.2018.8516763openalex-snapshot
Work-in-Progress: Writing-Aware Data Variable Allocation on Hybrid SRAM+NVM SPM
inferred← citeshttps://doi.org/10.1109/icassp.2013.6638129openalex-snapshot
Efficient task assignment and scheduling for MPSoC DSPS with VS-SPM considering concurrent accesses through data allocation
inferred← citeshttps://doi.org/10.1109/igcc.2015.7393714openalex-snapshot
Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach
inferred← citeshttps://doi.org/10.1109/nvmsa.2015.7304358openalex-snapshot
Exploring data placement in racetrack memory based scratchpad memory
inferred← citeshttps://doi.org/10.1109/rtest.2018.8397072openalex-snapshot
Fast write operations in non-volatile memories using latency masking
inferred← citeshttps://doi.org/10.1109/tc.2017.2703824openalex-snapshot
NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems
inferred← citeshttps://doi.org/10.1109/tc.2020.2988261openalex-snapshot
Fast and Predictable Non-Volatile Data Memory for Real-Time Embedded Systems
inferred← citeshttps://doi.org/10.1109/tcad.2014.2347929openalex-snapshot
A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems
inferred← citeshttps://doi.org/10.1109/tcsi.2017.2720678openalex-snapshot
Energy Optimization for Data Allocation With Hybrid SRAM+NVM SPM
inferred← citeshttps://doi.org/10.1109/tdmr.2017.2710089openalex-snapshot
OPTIMAS: Overwrite Purging Through In-Execution Memory Address Snooping to Improve Lifetime of NVM-Based Scratchpad Memories
inferred← citeshttps://doi.org/10.1109/tetc.2015.2398824openalex-snapshot
Data Allocation for Hybrid Memory With Genetic Algorithm
inferred← citeshttps://doi.org/10.1109/tetc.2018.2858020openalex-snapshot
High-Performance Predictable NVM-Based Instruction Memory for Real-Time Embedded Systems
inferred← citeshttps://doi.org/10.1109/tsusc.2021.3049447openalex-snapshot
MASTER: Reclamation of Hybrid Scratchpad Memory to Maximize Energy Saving in Multi-Core Edge Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2537400openalex-snapshot
Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory
inferred← citeshttps://doi.org/10.1145/2669556openalex-snapshot
Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy
inferred← citeshttps://doi.org/10.1145/3356583openalex-snapshot
Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design
inferred← citeshttps://doi.org/10.5555/3283552.3283563openalex-snapshot
Writing-aware data variable allocation on hybrid SRAM+NVM SPM: work-in-progress
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.