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Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_56openalex-snapshot
Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices
inferredcites →https://doi.org/10.1109/date.2003.1253622openalex-snapshot
Online scheduling for block-partitioned reconfigurable devices
inferredcites →https://doi.org/10.1109/icm.2010.5696192openalex-snapshot
An efficient scheduling methodology for heterogeneous multi-core processor systems
inferredcites →https://doi.org/10.1109/rtas.2006.10openalex-snapshot
Adaptive Allocation of Software and Hardware Real-Time Tasks for FPGA-based Embedded Systems
inferredcites →https://doi.org/10.1109/tc.2004.99openalex-snapshot
Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks
inferredcites →https://doi.org/10.1109/wises.2005.1438720openalex-snapshot
Periodic real-time scheduling for FPGA computers
inferredcites →https://doi.org/10.1201/9781420062670openalex-snapshot
Reconfigurable System Design and Verification
inferredcites →https://doi.org/10.1287/ijoc.1040.0106openalex-snapshot
Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-81-322-1602-5_10openalex-snapshot
A Novel Hardware/Software Partitioning Technique for System-on-Chip in Dynamic Partial Reconfiguration Using Genetic Algorithm
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.12.008openalex-snapshot
Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems
inferred← citeshttps://doi.org/10.1049/cje.2021.07.021openalex-snapshot
A Survey: FPGA‐Based Dynamic Scheduling of Hardware Tasks
inferred← citeshttps://doi.org/10.1109/ahs.2017.8046355openalex-snapshot
Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments
inferred← citeshttps://doi.org/10.1109/ahs.2017.8046358openalex-snapshot
Autonomic management of missions and reconfigurations in FPGA-based embedded system
inferred← citeshttps://doi.org/10.1109/dsd.2013.75openalex-snapshot
A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems
inferred← citeshttps://doi.org/10.1109/iccces62661.2026.11437104openalex-snapshot
Ravan 512 – A Dynamic Polymorpic Crypto Engine
inferred← citeshttps://doi.org/10.1109/reconfig.2013.6732331openalex-snapshot
SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function units
inferred← citeshttps://doi.org/10.1109/reconfig.2014.7032512openalex-snapshot
Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC
inferred← citeshttps://doi.org/10.1145/2927964.2927973openalex-snapshot
Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework
inferred← citeshttps://doi.org/10.1155/2014/164059openalex-snapshot
Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques
inferred← citeshttps://doi.org/10.1155/2016/9012909openalex-snapshot
An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems
inferred← citeshttps://doi.org/10.15587/1729-4061.2015.47227openalex-snapshot
Development of the reconfiguration acceleration method in the dynamically reconfigurable computing systems
inferred← citeshttps://doi.org/10.15587/1729-4061.2016.71460openalex-snapshot
The development of means of definition of the optimum ratio of computational algorithm and the reconfigurable structure
inferred← citeshttps://doi.org/10.15587/1729-4061.2016.81003openalex-snapshot
The method for providing quality of service time requirements in reconfigurable computing systems
inferred← citeshttps://doi.org/10.15587/1729-4061.2018.127361openalex-snapshot
Formalization of the concept of adaptive tasks mapping in the reconfigurable computers on FPGA
inferred← citeshttps://doi.org/10.18372/2073-4751.2.10868openalex-snapshot
The algorithm of preemptive reconfiguration for FPGA reconfigurable computer systems
inferred← citeshttps://doi.org/10.20535/2312-1807.2016.21.2.71110openalex-snapshot
Adaptive tasks mapping tools for reconfigurable computing structure in parallel computing systems under data flow control
inferred← citeshttps://doi.org/10.31174/nt2018-158vi18-14openalex-snapshot
The method of transforming algorithms’ graphs for tasks mapping in the dynamically reconfigurable computer systems
inferred← citeshttps://doi.org/10.32920/ryerson.14668209openalex-snapshot
A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors
inferred← citeshttps://doi.org/10.32920/ryerson.14668209.v1openalex-snapshot
A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors
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