On the public citation graph
CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search
0 signed · 72 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1049/iet-syb:20060038openalex-snapshot
Graph theory and networks in Biology
inferredcites →https://doi.org/10.1101/gr.074492.107openalex-snapshot
Velvet: Algorithms for de novo short read assembly using de Bruijn graphs
inferredcites →https://doi.org/10.1109/asap.2012.30openalex-snapshot
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration
inferredcites →https://doi.org/10.1109/asap.2013.6567573openalex-snapshot
Reduce, Reuse, Recycle (R3): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms
inferredcites →https://doi.org/10.1109/fccm.2011.60openalex-snapshot
A Sparse Matrix Personality for the Convey HC-1
inferredcites →https://doi.org/10.1109/fccm.2012.36openalex-snapshot
Hardware Acceleration of Short Read Mapping
inferredcites →https://doi.org/10.1109/fpl.2012.6339247openalex-snapshot
Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study
inferredcites →https://doi.org/10.1109/fpt.2010.5681757openalex-snapshot
A message-passing multi-softcore architecture on FPGA for Breadth-first Search
inferredcites →https://doi.org/10.1109/infcom.2010.5462078openalex-snapshot
Walking in Facebook: A Case Study of Unbiased Sampling of OSNs
inferredcites →https://doi.org/10.1109/ipdpsw.2013.159openalex-snapshot
Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search
inferredcites →https://doi.org/10.1109/mcse.2010.135openalex-snapshot
High-Performance Heterogeneous Computing with the Convey HC-1
inferredcites →https://doi.org/10.1109/mm.2010.36openalex-snapshot
Instruction Set Innovations for the Convey HC-1 Computer
inferredcites →https://doi.org/10.1109/pact.2011.14openalex-snapshot
Efficient Parallel Graph Exploration on Multi-Core CPU and GPU
inferredcites →https://doi.org/10.1109/sc.2010.46openalex-snapshot
Scalable Graph Exploration on Multicore Processors
inferredcites →https://doi.org/10.1109/sc.2012.25openalex-snapshot
Breaking the speed and scalability Barriers for Graph exploration on distributed-memory machines
inferredcites →https://doi.org/10.1109/sc.companion.2012.184openalex-snapshot
Abstract: Hybrid Breadth First Search Implementation for Hybrid-Core Computers
inferredcites →https://doi.org/10.1109/sc.companion.2012.185openalex-snapshot
Poster: Hybrid Breadth First Search Implementation for Hybrid-Core Computers
inferredcites →https://doi.org/10.1109/tpds.2013.111openalex-snapshot
Medusa: Simplified Graph Processing on GPUs
inferredcites →https://doi.org/10.1142/s0129626407002843openalex-snapshot
CHALLENGES IN PARALLEL GRAPH PROCESSING
inferredcites →https://doi.org/10.1145/1941553.1941590openalex-snapshot
Accelerating CUDA graph algorithms at maximum warp
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-981-16-0479-9_2openalex-snapshot
Distributed Graph Processing: Techniques and Systems
inferred← citeshttps://doi.org/10.1007/s11227-016-1712-0openalex-snapshot
Parallelized mining of domain knowledge on GPGPU and Xeon Phi clusters
inferred← citeshttps://doi.org/10.1007/s11390-019-1914-zopenalex-snapshot
A Survey on Graph Processing Accelerators: Challenges and Opportunities
inferred← citeshttps://doi.org/10.1007/s42514-020-00041-wopenalex-snapshot
Effective runtime scheduling for high-performance graph processing on heterogeneous dataflow architecture
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.04.010openalex-snapshot
A comprehensive reconfigurable computing approach to memory wall problem of large graph computation
inferred← citeshttps://doi.org/10.1088/1742-6596/1019/1/012036openalex-snapshot
Breadth First Search Approach for Shortest Path Solution in Cartesian Area
inferred← citeshttps://doi.org/10.1109/fccm.2016.35openalex-snapshot
High-Throughput and Energy-Efficient Graph Processing on FPGA
inferred← citeshttps://doi.org/10.1109/fpl.2015.7293939openalex-snapshot
Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform
inferred← citeshttps://doi.org/10.1109/fpl.2016.7577360openalex-snapshot
GraVF: A vertex-centric distributed graph processing framework on FPGAs
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00032openalex-snapshot
Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00016openalex-snapshot
GraphScale: Scalable Bandwidth-Efficient Graph Processing on FPGAs
inferred← citeshttps://doi.org/10.1109/hpcc-css-icess.2015.77openalex-snapshot
Addressing Memory Wall Problem of Graph Computation in Reconfigurable System
inferred← citeshttps://doi.org/10.1109/hpec.2015.7322439openalex-snapshot
Performance and productivity evaluation of hybrid-threading HLS versus HDLs
inferred← citeshttps://doi.org/10.1109/iccad.2015.7372588openalex-snapshot
CAMs as synchronizing caches for multithreaded irregular applications on FPGAs
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00056openalex-snapshot
OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs
inferred← citeshttps://doi.org/10.1109/ies55876.2022.9888418openalex-snapshot
Implementation of Air Quality Monitoring for Traffic Routing
inferred← citeshttps://doi.org/10.1109/ipdpsw.2015.130openalex-snapshot
Accelerating Large-Scale Single-Source Shortest Path on FPGA
inferred← citeshttps://doi.org/10.1109/ipdpsw52791.2021.00014openalex-snapshot
A Streaming Accelerator for Heterogeneous CPU-FPGA Processing of Graph Applications
inferred← citeshttps://doi.org/10.1109/reconfig.2015.7393284openalex-snapshot
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture
inferred← citeshttps://doi.org/10.1109/reconfig.2015.7393317openalex-snapshot
G-DMA: improving memory access performance for hardware accelerated sparse graph computation
inferred← citeshttps://doi.org/10.1109/reconfig.2015.7393332openalex-snapshot
Optimizing memory performance for FPGA implementation of pagerank
inferred← citeshttps://doi.org/10.1109/sbac-pad.2017.25openalex-snapshot
Accelerating Graph Analytics on CPU-FPGA Heterogeneous Platform
inferred← citeshttps://doi.org/10.1109/tcad.2017.2706562openalex-snapshot
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/tpds.2015.2407896openalex-snapshot
Suitability Analysis of FPGAs for Heterogeneous Platforms in HPC
inferred← citeshttps://doi.org/10.1145/2807700openalex-snapshot
A Reconfigurable Architecture for the Detection of Strongly Connected Components
inferred← citeshttps://doi.org/10.1145/3120895.3120896openalex-snapshot
Towards Flexible Automatic Generation of Graph Processing Gateware
inferred← citeshttps://doi.org/10.1145/3203217.3203233openalex-snapshot
An FPGA framework for edge-centric graph processing
inferred← citeshttps://doi.org/10.1145/3352460.3358318openalex-snapshot
Alleviating Irregularity in Graph Analytics Acceleration
inferred← citeshttps://doi.org/10.1145/3373376.3378482openalex-snapshot
A Hypervisor for Shared-Memory FPGA Platforms
inferred← citeshttps://doi.org/10.1145/3461837.3464512openalex-snapshot
Demystifying memory access patterns of FPGA-based graph processing accelerators
inferred← citeshttps://doi.org/10.1145/3466752.3480133openalex-snapshot
SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems
inferred← citeshttps://doi.org/10.1145/3503222.3507701openalex-snapshot
Debugging in the brave new world of reconfigurable hardware
inferred← citeshttps://doi.org/10.1145/3568990openalex-snapshot
Non-relational Databases on FPGAs: Survey, Design Decisions, Challenges
inferred← citeshttps://doi.org/10.1145/3582016.3582040openalex-snapshot
Vidi: Record Replay for Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1145/3587135.3592196openalex-snapshot
High-Level Synthesis of Irregular Applications
inferred← citeshttps://doi.org/10.1145/3626202.3637573openalex-snapshot
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
inferred← citeshttps://doi.org/10.1145/3648475openalex-snapshot
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources
inferred← citeshttps://doi.org/10.1145/3735452.3735533openalex-snapshot
Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation
inferred← citeshttps://doi.org/10.1360/n112018-00281openalex-snapshot
Memory system optimization for graph processing: a survey
inferred← citeshttps://doi.org/10.17760/d20474683openalex-snapshot
Partitioning data across multiple, network connected FPGAs with high bandwidth memory to accelerate non-streaming applications
inferred← citeshttps://doi.org/10.3390/electronics7110307openalex-snapshot
CGAcc: A Compressed Sparse Row Representation-Based BFS Graph Traversal Accelerator on Hybrid Memory Cube
inferred← citeshttps://doi.org/10.34133/2022/9806758openalex-snapshot
Software Systems Implementation and Domain-Specific Architectures towards Graph Analytics
inferred← citeshttps://doi.org/10.48550/arxiv.1903.06697openalex-snapshot
Graph Processing on FPGAs: Taxonomy, Survey, Challenges
inferred← citeshttps://doi.org/10.48550/arxiv.2010.14684openalex-snapshot
Substream-Centric Maximum Matchings on FPGA
inferred← citeshttps://doi.org/10.48550/arxiv.2105.11754openalex-snapshot
ScalaBFS: A Scalable BFS Accelerator on HBM-Enhanced FPGAs
inferred← citeshttps://doi.org/10.5555/2840819.2840866openalex-snapshot
CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.